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FSK technical question
Is anyone familiar with the hardware details of the FSK process?
Specifically what components are involved in transforming a frequency into a bit? Thanks! Dave |
#2
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David Harper ) writes: Is anyone familiar with the hardware details of the FSK process? Specifically what components are involved in transforming a frequency into a bit? Thanks! Dave It depends on how it's done. The earliest schemes were switching a capacitor in and out of the circuit of a VFO. I think they may have used relays originally, but once semiconductor diodes became common, they were used to do the switching. Apply a voltage, the diode conducts, and thus connects the capacitor into the circuit, lowering the frequency. When SSB came along, a common means was to feed an audio oscillator into the mic input, and that audio oscillator was shifted between two frequencies in the same way as above. Since a single tone in an SSB transmitter is the same as a cw transmitter (the transmitter translates the tone to a radio frequency), then shifting the audio oscillator shifts the transmitter between two distinct frequencies. This method was handy since it required no modification of the transmitter, and you got the same shift across the band. The previous scheme could not give the same shift as the vfo shifted frequency, since it was a fixed capacitor in parallel with the variable capacitor, so the fixed capacitor would give more shift as the frequency went up (since it was a larger percentage of the capacitance of the variable capacitor). The downside is that if the SSB transmitter wasn't adjusted for good carrier supression and unwanted sideband supression, or the audio oscillator did not put out a pure enough sinewave, then one would get more than a single frequency out of the transmitter. As an aside, on VHF AFSK (the shifting of an audio oscillator fed into the mic input of the transmitter) was pretty much the only scheme used for RTTY. Here, the result was not FSK, since you were using the regular modulation, AM or FM, of the transmitter. And the audio oscillator did not need to be as pure, since it didn't affect the spectrum of the transmitter. I actually don't know what the common scheme for FSK is these days. If the transmitter is using DSP, the fsk can be done digitally. I assume that DDS-based VFOs in current rigs may actually be able to be reprogrammed at a fast enough rate that one just keeps loading the two frequencies into the synthesizer as the shifting is needed, but I've not kept track of recent rigs to know if that's what's being used. Michael VE2BVW |
#3
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"Michael Black" wrote in message
... I actually don't know what the common scheme for FSK is these days. If the transmitter is using DSP, the fsk can be done digitally. I assume that DDS-based VFOs in current rigs may actually be able to be reprogrammed at a fast enough rate that one just keeps loading the two frequencies into the synthesizer as the shifting is needed, but I've not kept track of recent rigs to know if that's what's being used. This is pretty reasonable at low bit rates. But some more recent DDS chips, for example, TI's TRF4900, actually have a data pin, and the two frequencies are programmable, so the chip has the two divisors onboard making it a simple matter to switch between divisors. ... |
#4
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David Harper wrote:
Is anyone familiar with the hardware details of the FSK process? Specifically what components are involved in transforming a frequency into a bit? Thanks! Dave I think you already have a couple of messages on how the frequency can be generated from a bit. It appears to me you are asking for the opposite. Basically, the modem runs the receive frequencies through narrow filters. If the frequency received matches the passband of the filter, the audio tone gets through the filter. The tone can then drive something as simple as a transistor amplifier or darlington pair from one state to another (e.g. from Vc=5v to Vc=0.5v). These outputs can then drive gates in the right combination to get your serial output. What has changed over the past two decades is how the filters have been implemented and how the serial signal is generated. What used to be narrow filters built with big inductors and critical capacitors became filters implemented using op amps which, in turn, became filters using dsp techniques. Serial signal generation started out with straight off and on pulses to rtty ksrs, moved to simple uarts built with logic gates, which became uarts on ic's. The basics are the same, however. Narrow filters for the tones and logic to generate the serial signal. 73, tim a0bwr |
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tim gorman ) writes: David Harper wrote: Is anyone familiar with the hardware details of the FSK process? Specifically what components are involved in transforming a frequency into a bit? Thanks! Dave I think you already have a couple of messages on how the frequency can be generated from a bit. It appears to me you are asking for the opposite. You're right, I completely missed that. Michael VE2BVW |
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#7
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Ok, I have one more additional question. :-)
For a communications protocol such as RTTY, I know the mark and space frequencies indicate 0 and 1 values of a (usually) 5-bit character. But how does the receiving side synchronize with the transmitting side? How does the receiver continue to properly allocate the incoming bits? After, say, the 30th bit value, how does the receiver know that it *IS* the 30th bit value? Especially with three 1's or three 0's consecutively and no frequency changes...? Is the receiver just very accurately timed? When it occurs, do the transitions from 0's to 1's (and vice versa) serve to resynchronize the receiver with the transmitter? Sorry for the storm of questions, but thanks in advance! Dave |
#8
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----- Original Message -----
From: "David Harper" Subject: FSK technical question For a communications protocol such as RTTY, I know the mark and space frequencies indicate 0 and 1 values of a (usually) 5-bit character. But how does the receiving side synchronize with the transmitting side? How does the receiver continue to properly allocate the OK, remember the whole start and stop bit thing? The line sits at mark when idle. When a character comes, the line drops to space for one bit time. This is the start bit. Then the 5 or 8 bits are transmitted, then one, 1.5 or two stop bits, which are really nothing more than the minimum time between characters. So the receiver is guaranteed *at least* one bit time of mark followed by exactly one bit time of space between characters. The receiving side does need to be reasonably accurate, but only accurate enough to not garble a character. It never has to keep in sync for more than 10 bits worth (8 data bits plus a start and stop bit). If the protocol specifies more than one stop bit, from the receiver's perspective that is nothing more than additional time the transmitter has allotted to do end of character processing. On your earlier question about receiving FSK, the various posters answered what you would do if you wanted to use an SSB or AM rig, or an audio FM rig to receive FSK. However, a purpose-built FSK receiver would probably use an FM discriminator, and simply recover data, rather than audio, from the discriminator. Remember that an FM discriminator has an output that is related to the frequency. If you fed the discriminator two frequencies, the output would be two voltages. ... |
#9
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"David Harper" wrote in message
m... Ok, I have one more additional question. :-) Sorry, I skipped something on the previous response. I answered for ASYNCHRONOUS serial such as RTTY or async ASCII. Some protocols, such as packet, use SYNCHRONOUS serial. Synchronous serial is a lot harder to receive. There are no start and stop bits, so the protocol doesn't involve that part of the overhead that async uses. There are several synchronous protocols, but they mostly involve two characteristics.... first, there is some mechanism for the receiver to recover the clock. Frequently, the clock is embedded in the data, although is could be sent over another channel. This allows the receiver to know the bit boundaries. Every so often (typically every data packet) a special pattern is sent that allows the receiver to identify the character boundaries. In the common protocols, such as X.25 (or AX.25), there is also a prohibition against sending too many of the same bit in a row. Special procedures are invoked if this happens in the data. ... |
#10
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In (rec.radio.amateur.digital.misc), David Harper wrote:
Ok, I have one more additional question. :-) For a communications protocol such as RTTY, I know the mark and space frequencies indicate 0 and 1 values of a (usually) 5-bit character. But how does the receiving side synchronize with the transmitting side? How does the receiver continue to properly allocate the incoming bits? After, say, the 30th bit value, how does the receiver know that it *IS* the 30th bit value? Especially with three 1's or three 0's consecutively and no frequency changes...? Is the receiver just very accurately timed? When it occurs, do the transitions from 0's to 1's (and vice versa) serve to resynchronize the receiver with the transmitter? I don't view it as a storm of questions; I'd be surprised if anyone did, considering the floods asked by folks in some other newsgroups. Synchronization can be A Right Bitch. Good, Cheap Timing is part of the answer, and I think that the receivers also do some timebase adjustments as needed to keep their bit-rate clocks in sync with the transmitters'. When you add start and/or stop bit, things get a lot easier, and that is the case with most serial communications: you can reset the character and bit-time clocks per-character. When no sync bits are present, you have to derive the bit timing and character timing from the data-bit transitions in the data stream, and things can get a bit iffy. Telco circuits have hardware that requires K transitions per N bit times, and will stuff "1" or "0" bits into the stream on one end, and delete them on the other, before they get to the customer gear, so that the stream appears to be synchronous, even though it isn't really synchronous inside the telco circuit. But TY gear is _asynchronous_: it has bits to signal the start and end of each character. The general structure of a TTY character is Start_Bit, Data_Bits, Stop_Bit. The Start_Bit tells the machinery that there's a character coming down the pipe, and that it should get ready to move. When I was doing military communications, Way Back When, the start bit was a 1.5 bit time MARK, since there really were parts that had to get ready to move, clutches to engage, and so on, and the extra time ensured that things were ready when the first data bit came in. The stop bit was a 1.0 bit SPACE, IIRC, so that there was always a polarity change to signal a new character. But that's memories almost 40 years old, and I Could Be Wrong. Try this for more info: http://www.repairfaq.org/filipg/LINK/PORTS/F_The_Serial_Port1.html#THESERIALPORT_008 -- Mike Andrews Tired old sysadmin |
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