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Old August 5th 17, 05:05 PM posted to uk.radio.amateur,uk.rec.models.engineering,rec.radio.amateur.homebrew
Peter Fairbrother Peter Fairbrother is offline
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First recorded activity by RadioBanter: Aug 2017
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Default A mechanical phase locked loop!

On 05/08/17 16:19, rickman wrote:
Peter Fairbrother wrote on 8/5/2017 11:01 AM:
On 05/08/17 14:34, Chris wrote:

[..
The slave pendulum is kicked from time to time, and kicked a little more
often when the phases get too far apart - the difference in phases is the
error signal mentioned above - and these kicks do affect the phase of the
slave pendulum.


What they fail to see is that the amplitude of the kick *is* adjusted.
It's just the adjustment is binary, on or off. But that is still
*adjustment* and is in response to the measured phase.


Yup.

Compare with pwm (pulse width modulation) or ppm (pulse position
modulation) - I forget what the actual modulation in the clock is
called, but it is just another modulation, despite being binary and
fixed in amplitude.

A PLL does not necessarily keep the phase offset constant, just within
the interval +/- 2pi.


Not only that, but if you examine the equations for a PLL you will find
it is *impossible* to maintain a constant phase offset with any
variations in the reference or noise in the system.


Indeed.. in some ultimate sense, perhaps that is the final purpose of a
PLL.

ps; the +/- 2pi bit is not really a requirement either, as long as the
system can keep count of the missing/extra beats - but as most systems
don't
do that we shall just gracefully ignore that for now ..


In a typical PLL isn't the requirement to be within +/- pi rather than 2
pi? If you exceed a range of +/- pi from the intended alignment the
feedback will start to push the controlled oscillator further out of
alignment potentially aligning with another cycle of the master.


Yes, in a typical PLL - however I was considering a more theoretical one
where eg the phase offset was known to be positive or negative.



On reflection, is a system where the phases are several full cycles
out-of-phase, but where the system over time adjusts the slave to (close
to) the actual phase of the master, still a PLL?

On further reflection, I think it must be - so perhaps a better
definition might be that the integral of the phase difference remains
close to zero over long periods time (while leaving how close and how
long as an exercise for the reader) .

-- Peter F