All Digital Receiver (or nearly all digital)
 

"rickman" wrote in message
...
On 12/17/2012 10:18 PM, garyr wrote:

"Understanding Digital Signal Processing" by Richard G. Lyons is a good
source of information.

If you plan to do the FPGA code yourself check out: www.myhdl.org

For the antenna consider: www.febo.com/time-freq/wwvb/antenna

At 60 KHz RG-58 would be as good as RG-6 for a loop antenna and much
easier
to work with. PCV pipe is a good material for the frame. email me
directly
and I'll send you a photo of a 1m VLF antenna I made.

Unless you are located in Boulder, CO you will probably need an analog
amplifier.


Hi Gary,

Thanks for the info. I am familiar with Richard's book. He seems like a
good guy and will provide errata for anyone who has bought his book. I am
familiar with DSP in general and digital receivers specifically. I have
most of that part of the design analyzed enough to begin coding. It is the
ADC that I have had some trouble analyzing. I have been planning to
construct a Sigma-Delta converter in the FPGA. Turns out this might be a
little power hungry and I won't be able to use the special dithering that
shapes the noise. My primary goal is to do this entire project with very,
very little power consumption. If I can get a strong enough signal I can
just use an LVDS input without the integration of a Sigma-Delta converter,
but I won't know until I get some of this built and tested.

I am very experienced with HDL so I should be ok there.

I have found any number of sites that talk about loop antenna
construction, but most don't really explain how to analyze them. I have
finally cobbled together a good picture of the technical aspects from a
number of web sites and have an antenna plan. I am looking at using 50
feet of RG-6 with copper inner conductor to optimize the Q. My initial
pass is a compromise between optimizing the signal strength and making the
final unit easy to construct and support. It will be 8 turns on 2 foot
diameter wooden spokes. I expect the stiffness of the RG-6 to help
support the cable. This would likely be a decent design up to four foot
diameter.

In the end I may find I can use a ferrite loop. But the signal strengths
I have seen from commercial ferrite antennas do not seem to be good
enough, around 8 uV for 100uV/m field strength which is about what I
expect to see here on the east coast.

As to the amp, we will see. I have an equation to predict signal strength
at the antenna output and I am expecting a decent signal level if I have a
good Q and transformer couple the output. Total gain (Q and transformer)
over an untuned antenna will approach 10,000.

But there is many a slip between cup and lip. I hope to make some
progress on this over the holidays and have some test results.

Can you explain why you think RG-58 will be as good as the RG-6? The
inner conductor of RG-6 has only a small impact from skin effect, I think
it is around 21%. At 32 mil the inner conductor of RG-58 (compared to 40
mil for RG-6) will have even less impact from skin effect, but will have a
higher resistance and so a lower Q. The capacitance per foot is nearly
twice that of RG-6 as well although I'm still not clear on the specific
details of this effect. I believe higher capacitance will lower the self
resonant frequency although I don't expect this to be a problem in my
application.

Rick

I don't understand how you intend to use an LVDS input for the WWVB signal?
Could you explain.

Have you considered using a WWVB receiver IC? I don't know what kind of
power they require but they generate the 1pps PWM signal which could be
processed by a low-power microprocessor very easily.

http://www.c-max-time.com/products/showProduct.php?id=2
http://www.pvelectronics.co.uk/index...&products_id=7
http://www.ntp-time-server.com/wwvb-...b-receiver.htm

I've constructed loop antennas using both RG-58 (60 KHz) and RG-6, or
something similar to RG-6 (~20 KHz) and had good luck with both. I haven't
compared the outputs of both tuned to 60 KHz so I can't say much about how
their electrical performance compare. The RG-6 with the aluminum shield is a
PITA
because you can't make a solder connection to it. Self-resonance will not be
a problem. 100' of RG-58 on a 1 meter dia. frame required about 25 nF to
resonate at 60 KHz. One advantage of the febo-type antenna with the 1-turn
pickup loop is that its output impedance is very low which means that the
antenna can be located away from the receiver.

All Digital Receiver (or nearly all digital)
 

On 12/19/2012 10:26 AM, garyr wrote:

I don't understand how you intend to use an LVDS input for the WWVB signal?
Could you explain.

I guess you didn't read my initial post. My intent is to create an
all-digital receiver at very low power. The receiver ICs around use
standard analog technology to detect the AM signal. WWVB has added
phase modulation which should be receivable at a lower SNR. I also want
to detect both modulation schemes and compare the results.


Have you considered using a WWVB receiver IC? I don't know what kind of
power they require but they generate the 1pps PWM signal which could be
processed by a low-power microprocessor very easily.

They are fairly low power as can be CPU chips when cycled on and off as
needed. But I want to do this in an FPGA so I can see just how low
power it can be.


http://www.c-max-time.com/products/showProduct.php?id=2
http://www.pvelectronics.co.uk/index...&products_id=7
http://www.ntp-time-server.com/wwvb-...b-receiver.htm

I've constructed loop antennas using both RG-58 (60 KHz) and RG-6, or
something similar to RG-6 (~20 KHz) and had good luck with both. I haven't
compared the outputs of both tuned to 60 KHz so I can't say much about how
their electrical performance compare. The RG-6 with the aluminum shield is a
PITA
because you can't make a solder connection to it. Self-resonance will not be
a problem. 100' of RG-58 on a 1 meter dia. frame required about 25 nF to
resonate at 60 KHz. One advantage of the febo-type antenna with the 1-turn
pickup loop is that its output impedance is very low which means that the
antenna can be located away from the receiver.

The cable I have already has F type connectors on the ends, so I don't
care about the aluminum shield. I did have to shop around a bit to find
one with an all copper inner conductor. Seems they use copper coated
steel for CATV. I think my numbers are for a bit less than 80 nF of
capacitance so I bought a bunch of 15 nF silver mica parts and some
other small values to tune it in closely, then I have a triple bank,
0-500 pF tuner cap from an old receiver for final tuning. Once I have
the rest of the system working well, I'll likely use fixed values of
caps to tune the antenna without the variable cap. I saw one antenna
that used a bank of roughly power of 2 caps with switches to allow the
antenna to be tuned easily, cute.

I am thinking of using a ferrite core as a coupling transformer as it
will give me a lot of voltage gain. I am looking to get towards 10,000
gain from combined Q and transformer.

The LVDS input on the FPGA will act as a 1 bit ADC. I was planning to
use this in a Sigma-Delta converter and produce a 4 bit value at 240 kHz
(4x carrier rate). I'm not sure I need the Sigma-Delta converter and
might end up just using the 1 bit from the LVDS directly. By
downconverting to DC and downsampling to 30 Hz I will get a *lot* of
processing gain with an SNR improvement of some 33 dB (assuming
uncorrelated noise). Another way to look at the digital design is as a
very long FIR filter resulting in a filter with a very narrow bandpass
or one bin of a DFT. Turns out they are all the same math in this case
(multiply by 1, 0, -1, 0 sequence).

There are a few wrinkles I haven't figured out yet. I need a sample
clock that is both accurate and low power. I have yet to find that. XO
oscillators I have found over 1 MHz are all in the mA range. I'm
thinking of using the very poor internal oscillator in the FPGA and
calibrating it to a 32.768 kHz reference which can be both accurate and
low power. But I don't yet know if the internal oscillator is low power
enough. I need to fire up the eval board (gratis from NuHorizons) and
measure the power consumption with and without the internal oscillator
enabled. If the power consumption is low enough I can frequency lock it
to the clock oscillator and come up with a calibration factor. Then the
sample clock can be generated internally using a DCO updated with each
calibration.

Thanks for discussing this with me. I like to bounce ideas off of other
people.

Rick

All Digital Receiver (or nearly all digital)
 

I thought I would cross post this to rec.radio.amateur.moderated. They
have made a number of announcements about this and seem to be
encouraging the practice.

Rick


On 12/19/2012 3:51 PM, rickman wrote:
On 12/19/2012 10:26 AM, garyr wrote:

I don't understand how you intend to use an LVDS input for the WWVB
signal?
Could you explain.

I guess you didn't read my initial post. My intent is to create an
all-digital receiver at very low power. The receiver ICs around use
standard analog technology to detect the AM signal. WWVB has added phase
modulation which should be receivable at a lower SNR. I also want to
detect both modulation schemes and compare the results.


Have you considered using a WWVB receiver IC? I don't know what kind of
power they require but they generate the 1pps PWM signal which could be
processed by a low-power microprocessor very easily.

They are fairly low power as can be CPU chips when cycled on and off as
needed. But I want to do this in an FPGA so I can see just how low power
it can be.


http://www.c-max-time.com/products/showProduct.php?id=2
http://www.pvelectronics.co.uk/index...&products_id=7

http://www.ntp-time-server.com/wwvb-...b-receiver.htm

I've constructed loop antennas using both RG-58 (60 KHz) and RG-6, or
something similar to RG-6 (~20 KHz) and had good luck with both. I
haven't
compared the outputs of both tuned to 60 KHz so I can't say much about
how
their electrical performance compare. The RG-6 with the aluminum
shield is a
PITA
because you can't make a solder connection to it. Self-resonance will
not be
a problem. 100' of RG-58 on a 1 meter dia. frame required about 25 nF to
resonate at 60 KHz. One advantage of the febo-type antenna with the
1-turn
pickup loop is that its output impedance is very low which means that the
antenna can be located away from the receiver.

The cable I have already has F type connectors on the ends, so I don't
care about the aluminum shield. I did have to shop around a bit to find
one with an all copper inner conductor. Seems they use copper coated
steel for CATV. I think my numbers are for a bit less than 80 nF of
capacitance so I bought a bunch of 15 nF silver mica parts and some
other small values to tune it in closely, then I have a triple bank,
0-500 pF tuner cap from an old receiver for final tuning. Once I have
the rest of the system working well, I'll likely use fixed values of
caps to tune the antenna without the variable cap. I saw one antenna
that used a bank of roughly power of 2 caps with switches to allow the
antenna to be tuned easily, cute.

I am thinking of using a ferrite core as a coupling transformer as it
will give me a lot of voltage gain. I am looking to get towards 10,000
gain from combined Q and transformer.

The LVDS input on the FPGA will act as a 1 bit ADC. I was planning to
use this in a Sigma-Delta converter and produce a 4 bit value at 240 kHz
(4x carrier rate). I'm not sure I need the Sigma-Delta converter and
might end up just using the 1 bit from the LVDS directly. By
downconverting to DC and downsampling to 30 Hz I will get a *lot* of
processing gain with an SNR improvement of some 33 dB (assuming
uncorrelated noise). Another way to look at the digital design is as a
very long FIR filter resulting in a filter with a very narrow bandpass
or one bin of a DFT. Turns out they are all the same math in this case
(multiply by 1, 0, -1, 0 sequence).

There are a few wrinkles I haven't figured out yet. I need a sample
clock that is both accurate and low power. I have yet to find that. XO
oscillators I have found over 1 MHz are all in the mA range. I'm
thinking of using the very poor internal oscillator in the FPGA and
calibrating it to a 32.768 kHz reference which can be both accurate and
low power. But I don't yet know if the internal oscillator is low power
enough. I need to fire up the eval board (gratis from NuHorizons) and
measure the power consumption with and without the internal oscillator
enabled. If the power consumption is low enough I can frequency lock it
to the clock oscillator and come up with a calibration factor. Then the
sample clock can be generated internally using a DCO updated with each
calibration.

Thanks for discussing this with me. I like to bounce ideas off of other
people.

Rick