Typically the DDS is used as the reference oscillator for the PLL, resulting
in the VCO being at a multiple of the DDS output frequency. The idea being
that the VCO output will have decent phase noise performance with the fine
frequency resolution of the DDS, and resaonably fast stepping times---"the
best of both worlds", you might say.

I discovered an interesting alternative at :
http://lea.hamradio.si/~s57nan/ham_r.../dds_9851.html



This idea has the DDS acting as a programmable divider inside the PLL
feedback loop. Ok, what are the advantages or disadvantages of doing this?
What does it do to the phase noise and lock-up time? And what about the
spurs?



Jim

N8EE

Typically the DDS is used as the reference oscillator for the PLL, resulting
in the VCO being at a multiple of the DDS output frequency. The idea being
that the VCO output will have decent phase noise performance with the fine
frequency resolution of the DDS, and resaonably fast stepping times---"the
best of both worlds", you might say.

I discovered an interesting alternative at :
http://lea.hamradio.si/~s57nan/ham_r.../dds_9851.html



This idea has the DDS acting as a programmable divider inside the PLL
feedback loop. Ok, what are the advantages or disadvantages of doing this?
What does it do to the phase noise and lock-up time? And what about the
spurs?

Spurious are down to normal analogue pll levels.

As is phase noise.

Lock-up time is somewhat slower than the DDS, this is reduced down to normal PLL
times as well.

Doing it this way gives you one advantage over a normal analogue pll - small
frequency steps ( = normal analogue pll with fractional divider).

Clive

Check http://www.qsl.net/ke5fx/synth.html
for a 1-2 GHz design using DDS/PLL technology

wrote in message
...

Typically the DDS is used as the reference oscillator for the PLL,
resulting
in the VCO being at a multiple of the DDS output frequency. The idea
being
that the VCO output will have decent phase noise performance with the
fine
frequency resolution of the DDS, and resaonably fast stepping
times---"the
best of both worlds", you might say.

I discovered an interesting alternative at :
http://lea.hamradio.si/~s57nan/ham_r.../dds_9851.html



This idea has the DDS acting as a programmable divider inside the PLL
feedback loop. Ok, what are the advantages or disadvantages of doing
this?

At the frequencies we used it would have been necessary to use a prescaler
in front of the DDS. The newer chips seem to be getting up towards a 1GHz
clock rate, so this might be an option

What does it do to the phase noise and lock-up time? And what about the
spurs?

Spurious are down to normal analogue pll levels.

We found in our design that phase noise was attenuated by the loop inside
the loop bandwidth, but was dependent on the quality of the VCO outside
this. The PLL is sensitive to any spurs on its reference and multiplies them
by 20 Log N dB, where N is the loop division ratio. This applies near the
comparison freq and at harmonics of the comparison freq. So you have to
severely band limit the output of the DDS. If it were in a loop with a
constant reference freq output, you could get even better band limiting, so
this problem might be reduced. Alternatively, the loop filter would get rid
of wideband spurs. Another advantage would be that the computation of output
frequency would be somewhat simpler than with the other appraoch

Does anyone have a pointer to a detailed analysis of this approach?

Richard


As is phase noise.

Lock-up time is somewhat slower than the DDS, this is reduced down to
normal PLL
times as well.

Doing it this way gives you one advantage over a normal analogue pll -
small
frequency steps ( = normal analogue pll with fractional divider).

Clive

Check http://www.qsl.net/ke5fx/synth.html
for a 1-2 GHz design using DDS/PLL technology

wrote in message
...

Typically the DDS is used as the reference oscillator for the PLL,
resulting
in the VCO being at a multiple of the DDS output frequency. The idea
being
that the VCO output will have decent phase noise performance with the
fine
frequency resolution of the DDS, and resaonably fast stepping
times---"the
best of both worlds", you might say.

I discovered an interesting alternative at :
http://lea.hamradio.si/~s57nan/ham_r.../dds_9851.html



This idea has the DDS acting as a programmable divider inside the PLL
feedback loop. Ok, what are the advantages or disadvantages of doing
this?

At the frequencies we used it would have been necessary to use a prescaler
in front of the DDS. The newer chips seem to be getting up towards a 1GHz
clock rate, so this might be an option

What does it do to the phase noise and lock-up time? And what about the
spurs?

Spurious are down to normal analogue pll levels.

We found in our design that phase noise was attenuated by the loop inside
the loop bandwidth, but was dependent on the quality of the VCO outside
this. The PLL is sensitive to any spurs on its reference and multiplies them
by 20 Log N dB, where N is the loop division ratio. This applies near the
comparison freq and at harmonics of the comparison freq. So you have to
severely band limit the output of the DDS. If it were in a loop with a
constant reference freq output, you could get even better band limiting, so
this problem might be reduced. Alternatively, the loop filter would get rid
of wideband spurs. Another advantage would be that the computation of output
frequency would be somewhat simpler than with the other appraoch

Does anyone have a pointer to a detailed analysis of this approach?

Richard


As is phase noise.

Lock-up time is somewhat slower than the DDS, this is reduced down to
normal PLL
times as well.

Doing it this way gives you one advantage over a normal analogue pll -
small
frequency steps ( = normal analogue pll with fractional divider).

Clive

Typically the DDS is used as the reference oscillator for the PLL, resulting
in the VCO being at a multiple of the DDS output frequency. The idea being
that the VCO output will have decent phase noise performance with the fine
frequency resolution of the DDS, and resaonably fast stepping times---"the
best of both worlds", you might say.

I discovered an interesting alternative at :
http://lea.hamradio.si/~s57nan/ham_r.../dds_9851.html



This idea has the DDS acting as a programmable divider inside the PLL
feedback loop. Ok, what are the advantages or disadvantages of doing this?
What does it do to the phase noise and lock-up time? And what about the
spurs?

Spurious are down to normal analogue pll levels.

As is phase noise.

Lock-up time is somewhat slower than the DDS, this is reduced down to normal PLL
times as well.

Doing it this way gives you one advantage over a normal analogue pll - small
frequency steps ( = normal analogue pll with fractional divider).

Clive

JLB wrote:
Typically the DDS is used as the reference oscillator for the PLL, resulting
in the VCO being at a multiple of the DDS output frequency. The idea being
that the VCO output will have decent phase noise performance with the fine
frequency resolution of the DDS, and resaonably fast stepping times---"the
best of both worlds", you might say.

I discovered an interesting alternative at :
http://lea.hamradio.si/~s57nan/ham_r.../dds_9851.html



This idea has the DDS acting as a programmable divider inside the PLL
feedback loop. Ok, what are the advantages or disadvantages of doing this?
What does it do to the phase noise and lock-up time? And what about the
spurs?



Jim

N8EE


There are several ways to combine the dds and pll.
If you do it this way, by using the dds as the divider in a pll circuit
your dds must accept the clock rate of the pll output frequency. DDS
circuits that operate at clock rates as high as 400mhz are now common.
The software to calculate the divisor constant for the dds given the
desired pll output frequency might involve floating point math, I briefly
looked at it and didn't see a clear way to do it with integers using an
8051.

Another circuit uses the dds to provide the reference (R) for the phase
comparater of the PLL and setting the output frequency is now a matter of
selecting the PLL divisor ratio and the reference frequency. The DDS
provides
the fine tuning, and the PLL the course adjustment. I worked up a
design where
the reference for the PLL was nominally around 100khz (actually 64 or 128khz
so it would be an even power of two). Then the software was an integer math
problem, though it did require either integer multiplication or
division. I was
able to invert the problem so only integer multiplication was required, and
a table driven routine will work fine on the 8051. In fact, I was able
to insert the
IF offset into the tables, and all the routines are in binary, NOT BCD.
A binary
to bcd conversion is required to display the frequency, and bcd to binary is
needed for keypad entry, but the rotary shaft encoder could drive in binary.

If anyone has build a radio using a dds/pll vfo, I'd like to know how
they handled
the user interface in software, which micros they used and how they
handled the
math to calculate the divisor constants.

If anyone has build a radio using a dds/pll vfo, I'd like to know how
they handled
the user interface in software, which micros they used and how they
handled the
math to calculate the divisor constants.

Heres the way I do a simple integer division ...

j = i / 0.66 ... that's what we want, both i & j are int's

The same as ..

j = i * (1 / 0.66)

The same as ..

j = i * 1.5151

Have the 1.5151 as a look up in rom but scaled up by *256 (388 in int terms)

So you have ..

j = i * 388

Then you divide the result by 256 (a simple shift right by 8 bits)


eg ..

i = 54
i = i * 388
j = i asr 8 .... this gets rid of the scale up

or

j = i shr 8 .... for unsigned calcs

..

j now equals 82 (as near as you can get to 81.84375)


If the divisor is variable then you prolly have no choice but to do a proper
division at some point, but still use scaled up int's to get your result.


Clive

If anyone has build a radio using a dds/pll vfo, I'd like to know how
they handled
the user interface in software, which micros they used and how they
handled the
math to calculate the divisor constants.

Heres the way I do a simple integer division ...

j = i / 0.66 ... that's what we want, both i & j are int's

The same as ..

j = i * (1 / 0.66)

The same as ..

j = i * 1.5151

Have the 1.5151 as a look up in rom but scaled up by *256 (388 in int terms)

So you have ..

j = i * 388

Then you divide the result by 256 (a simple shift right by 8 bits)


eg ..

i = 54
i = i * 388
j = i asr 8 .... this gets rid of the scale up

or

j = i shr 8 .... for unsigned calcs

..

j now equals 82 (as near as you can get to 81.84375)


If the divisor is variable then you prolly have no choice but to do a proper
division at some point, but still use scaled up int's to get your result.


Clive

JLB wrote:
Typically the DDS is used as the reference oscillator for the PLL, resulting
in the VCO being at a multiple of the DDS output frequency. The idea being
that the VCO output will have decent phase noise performance with the fine
frequency resolution of the DDS, and resaonably fast stepping times---"the
best of both worlds", you might say.

I discovered an interesting alternative at :
http://lea.hamradio.si/~s57nan/ham_r.../dds_9851.html



This idea has the DDS acting as a programmable divider inside the PLL
feedback loop. Ok, what are the advantages or disadvantages of doing this?
What does it do to the phase noise and lock-up time? And what about the
spurs?



Jim

N8EE


There are several ways to combine the dds and pll.
If you do it this way, by using the dds as the divider in a pll circuit
your dds must accept the clock rate of the pll output frequency. DDS
circuits that operate at clock rates as high as 400mhz are now common.
The software to calculate the divisor constant for the dds given the
desired pll output frequency might involve floating point math, I briefly
looked at it and didn't see a clear way to do it with integers using an
8051.

Another circuit uses the dds to provide the reference (R) for the phase
comparater of the PLL and setting the output frequency is now a matter of
selecting the PLL divisor ratio and the reference frequency. The DDS
provides
the fine tuning, and the PLL the course adjustment. I worked up a
design where
the reference for the PLL was nominally around 100khz (actually 64 or 128khz
so it would be an even power of two). Then the software was an integer math
problem, though it did require either integer multiplication or
division. I was
able to invert the problem so only integer multiplication was required, and
a table driven routine will work fine on the 8051. In fact, I was able
to insert the
IF offset into the tables, and all the routines are in binary, NOT BCD.
A binary
to bcd conversion is required to display the frequency, and bcd to binary is
needed for keypad entry, but the rotary shaft encoder could drive in binary.

If anyone has build a radio using a dds/pll vfo, I'd like to know how
they handled
the user interface in software, which micros they used and how they
handled the
math to calculate the divisor constants.