PLL for VHF receiver (see attached files)
Hello everybody,
I have build a VHF receiver for the airband, published in the magazine Elektor a few years ago, and I've managed to build a PLL to improve it. The PLL is build on another PCB, that is connected to the main circuit, and that replaces the original potmeter, in order to choose the frequency. The PLL is able to lock on the right frequency, but the receiver is a lot more noisy, and it seems really less sensitive with the PLL. See these sketches, I think it is better than a long explaination. http://www.mcarsweb.com/_divers/1sketch.jpg http://www.mcarsweb.com/_divers/2sketch.jpg http://www.mcarsweb.com/_divers/3sketch.jpg I have also included the schematics of the VCO (with the buffering transistor, T4), and the basic schematic of the PLL (taken from a Motorola application note). I don't know where the problem could come from. I would say from the bad buffering of the VCO output, but I don't see how it could be improved. http://www.mcarsweb.com/_divers/4VCO.jpg http://www.mcarsweb.com/_divers/5PLL.jpg I'm really getting mad with this problem ! So thanks to all of you who will answer ;-) |
"Damien Teney" wrote in message
... I have also included the schematics of the VCO (with the buffering transistor, T4), and the basic schematic of the PLL (taken from a Motorola application note). I don't know where the problem could come from. I would say from the bad buffering of the VCO output, but I don't see how it could be improved. http://www.mcarsweb.com/_divers/4VCO.jpg http://www.mcarsweb.com/_divers/5PLL.jpg I'm really getting mad with this problem ! So thanks to all of you who will answer ;-) What's your reference frequency? I mean, prescaler ratio and pll step. SioL |
Hi,
Did you build the loop filter per the schematic in that app note? Have you put a 10X scope probe on the VCO control line and viewed it with a scope? Also, where did you find that PLL app note? It looks much like others I have seen from Motorola on that series of PLL but I'm always looking for more documentation. :) 72 Bob WB0POQ |
What's your reference frequency? I mean, prescaler ratio and pll step.
Reference frequency is given by a 5.12 MHz crystal, divided by 1024, that makes 5 KHz steps. The prescaler divides by 64/65. |
Hi,
Did you build the loop filter per the schematic in that app note? Have you put a 10X scope probe on the VCO control line and viewed it with a scope? In fact the problem is that the receiver is less sensitive and products a lot of whistles, even when I ONLY connect the output of the VCO to the PLL, and control it with the potmeter (see http://www.mcarsweb.com/_divers/3sketch.jpg). That shows that the problem cannot be in the output filter of the PLL. I have also tried to put the PLL circuit alone in a grounded closed metal box to shield it, but I still get these whistles in the receiver output. Where do you think the problem could come from ? where did you find that PLL app note? It looks much like others I have seen from Motorola on that series of PLL but I'm always looking for more documentation. :) Motorola application note 980 http://www.mcarsweb.com/_divers/Moto...note%20980.pdf |
"Damien Teney" wrote in message
om... What's your reference frequency? I mean, prescaler ratio and pll step. Reference frequency is given by a 5.12 MHz crystal, divided by 1024, that makes 5 KHz steps. The prescaler divides by 64/65. I see others in sed have given valuable advice. Seems like shielding will improve things. One other thing, try to power the radio and the PLL from different sources just for a test. You'll need good power decoupling to eliminate spikes generated by the PLL circuitry. SioL |
Damien Teney wrote: In fact the problem is that the receiver is less sensitive and products a lot of whistles, even when I ONLY connect the output of the VCO to the PLL, and control it with the potmeter (see http://www.mcarsweb.com/_divers/3sketch.jpg). That shows that the problem cannot be in the output filter of the PLL. I see....Ok, sounds like the trouble is in the VCO itself or in how the VCO is coupled to the mixer. Do you have access to a spectrum analyzer? It is beginning to sound like the oscillator may have a dirty output or what used to be called 'squeegging' (sp?). Here are some things I would try. Use a couple of resistors to set the DC voltage on the varactor to some moderate value. Make double-dog-darn-sure that the DC voltage feeding the VCO and the varactor are absolutely clean (with a scope). See if problem persists. (Obviously you will be at a fixed frequency here). If so, I would suspect the oscillator problem described above. Perhaps less feedback, or running it at a lower value of Vcc might help. I think you said that the basic rx worked fine with a different LO. Is this the case? If so, check the output of that LO with a scope or RF probe and see if your VCO output is a similar P-P value. Maybe you are overdriving the mixer? My gut feeling is that the problem will turn out to be a noisy DC control line on the varactor or dirty output from the oscillator. Best of luck. Lets us know what you come up with. Remember.....this kind of thing builds character and troubleshooting skills! :) These are just basic troubleshooting ideas, but might lead you to something meaningful. I have also tried to put the PLL circuit alone in a grounded closed metal box to shield it, but I still get these whistles in the receiver output. Where do you think the problem could come from ? where did you find that PLL app note? It looks much like others I have seen from Motorola on that series of PLL but I'm always looking for more documentation. :) Motorola application note 980 http://www.mcarsweb.com/_divers/Moto...note%20980.pdf |
the crucial piece of information is that noise stays even when you
have opened up the VCO loop. looking at your setup, it appears to me that the noise can come from two sources, a) the VCO and b) the PLL. evidentaly, it is not from the VCO as your experiments prove. it is probably from the PLL circuitry. this is quite possible. the PLLs involve a lot of digital, noisy switching that can generate these birdies and spurs. however, these should stay well inside the PLL block. in your case, they are getting coupled back to your output. there are a number of cures for this. all of them will work at a better buffer between the vco and the following PLL. the simplest solution is use a grounded gate FET amplifier between the PLL input and the VCO output. be careful though, such a configuration is almost gaurenteed to self oscillate. but that is easily taken care of. what you do is this .. solder the FET upside down with its legs sticking up. solder the gate to the ground with as small a lead as you can. then, using a thin copper sheet or an unetched pcb, make a sheild that is soldered vertically over the FET (with a cutaway to allow the FET body). keep the source and drain leads on opposite sides of the sheild. bias the FET for nominal current at about half the Idss. if you have a copy of EMRFD around, you can check this design in the chapter on oscillators. - farhan |
all of them will work at a
better buffer between the vco and the following PLL. the simplest solution is use a grounded gate FET amplifier between the PLL input and the VCO output. be careful though, such a configuration is almost gaurenteed to self oscillate. but that is easily taken care of. what you do is this .. solder the FET upside down with its legs sticking up. solder the gate to the ground with as small a lead as you can. then, using a thin copper sheet or an unetched pcb, make a sheild that is soldered vertically over the FET (with a cutaway to allow the FET body). keep the source and drain leads on opposite sides of the sheild. bias the FET for nominal current at about half the Idss. Yes, that also sounds for me the best thing to do (improving buffer between VCO and PLL). Well, I'm not experienced with such circuits, so could you just explain how to bias the FET. VCO o-||-- S-D --||--o OUT TO PLL ^ FET=MPF102 or stg like that G | o----------------o GND And one last thing, could you re-explain how you advise to shield the FET ? I don't see what you mean :-( Thanks for your answer ;-) |
If anyone else has got the answer, come on, post !
Yes, that also sounds for me the best thing to do (improving buffer between VCO and PLL). Well, I'm not experienced with such circuits, so could you just explain how to bias the FET. VCO o-||-- S-D --||--o OUT TO PLL ^ FET=MPF102 or stg like that G | o----------------o GND And one last thing, could you re-explain how you advise to shield the FET ? I don't see what you mean :-( Thanks for your answer ;-) |
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Thanks I've understood what you mean ;-)
bias the FET for nominal current at about half the Idss. As I'm not (yet) familiar with such circuits, so could you tell me how to do this :-$ ? Thanks. Damien |
In article ,
Ashhar Farhan wrote: let me explain this a little more visually. to begin with, i imagine that you are building this ugly style over a copper clad board. Now, imagine that you have soldered another piece of copper clad board (about an inch high and 2 inches across) so that stands vertically at ninety degrees from the base board. Now imagine that you have cut out a small mouse hole in this 'wall'. The size of the mouse hole is just enough to let the FET's body (and not the leads) pass through. You take an FET, bend its drain and source to ninety degrees and away from the FET body. Now you slide the FET into the mouse hole. Bend down the gate and solder it to the base copper clad board.The source and drain leads should be on either sides of this wall (the sheild). this will prevent the source and drain from coupling the energy back to each other. A slight variation on this approach, which I've seen recommended for use with U310 (TO-52 metal case) is to actually drill a small hole downwards through the "ugly-style" copperclad, just barely large enough to admit the body of the JFET. Drop the JFET into the hole - it's fine if the metal case contacts the copper, as the case and gate are connected together. Bend the source and drain out sidewise, leave the gate lead sticking up in the air, put the shielding piece of copperclad with the "mouse hole" into place, solder it to the board, and then solder the gate lead to the copperclad on one side of the shield. This results in a very short, low-inductance connection of the gate to ground. This technique would probably work just about as well with a J310 or similar TO-92 plastic-package JFET, although it won't give the additional benefit of grounding/shielding via the metal case. As to the U310 - anyone know of a convenient source? I haven't seen anyone selling old-stock U310s on the Net, and there's only one manufacturer I know of making them (Linear Systems). -- Dave Platt AE6EO Hosting the Jade Warrior home page: http://www.radagast.org/jade-warrior I do _not_ wish to receive unsolicited commercial email, and I will boycott any company which has the gall to send me such ads! |
"Damien Teney" wrote in message ...
Thanks I've understood what you mean ;-) bias the FET for nominal current at about half the Idss. As I'm not (yet) familiar with such circuits, so could you tell me how to do this :-$ ? Thanks. Damien W7ZOI has a quick and dirty way of finding this out. 1) Connect a 1K resistor from the drain of the FET to 12v power supply. 2) solder a 10K resistor from the source of the FET to ground. 3) ground the gate 4) apply power and measure the voltage on the source. this gives you the pinchoff voltage (Vp). 5) short the source to the ground as well. Meausre the current flowing through the drain (you can measure the voltage between the drain and the 12v supply and divide it by 1000). This current value is IDss. Now, choose a source resistor of the value Vp/(Idss * 4). btw, you can simpley chuck all this and try 560 ohms. it should work ;). the gain, noise figure etc are not too crucial. the idea is to buffer the input and output. - farhan - farhan |
Okay, but that stuff is only used to find out the Vp and Idss I guess ?
So the "amplifier" itself is only made up of the FET, with the gate grounded, the drain as output, and the source as input via 1 resistor (560 ohms) ? Damien PS: that's probably the last question ;-) W7ZOI has a quick and dirty way of finding this out. 1) Connect a 1K resistor from the drain of the FET to 12v power supply. 2) solder a 10K resistor from the source of the FET to ground. 3) ground the gate 4) apply power and measure the voltage on the source. this gives you the pinchoff voltage (Vp). 5) short the source to the ground as well. Meausre the current flowing through the drain (you can measure the voltage between the drain and the 12v supply and divide it by 1000). This current value is IDss. Now, choose a source resistor of the value Vp/(Idss * 4). btw, you can simpley chuck all this and try 560 ohms. it should work ;). the gain, noise figure etc are not too crucial. the idea is to buffer the input and output. - farhan |
There are a few possible sources of problems
(1) Power supply for the PLL and VCO - noise on these will appear in the output. use separate supplies with ?zeners rather than IC regulators (2) Is the amplitude from the buffer enough to drive the prescaler properly? (3) Is the loop stable - how did you arrive at your calculations for the loop values? (4) The VCO tank seems to be heavily loaded - it has an output directly to the Rx and a large (68p) capacitor to the varicap which is low Q. This would make it noisier. Why not take the output to the Rx from the buffer? (is that how it was originally?) Also could you use a smaller cap to the varicap? (say 5p or less) Richard Damien Teney wrote: Hello everybody, I have build a VHF receiver for the airband, published in the magazine Elektor a few years ago, and I've managed to build a PLL to improve it. The PLL is build on another PCB, that is connected to the main circuit, and that replaces the original potmeter, in order to choose the frequency. The PLL is able to lock on the right frequency, but the receiver is a lot more noisy, and it seems really less sensitive with the PLL. See these sketches, I think it is better than a long explaination. http://www.mcarsweb.com/_divers/1sketch.jpg http://www.mcarsweb.com/_divers/2sketch.jpg http://www.mcarsweb.com/_divers/3sketch.jpg I have also included the schematics of the VCO (with the buffering transistor, T4), and the basic schematic of the PLL (taken from a Motorola application note). I don't know where the problem could come from. I would say from the bad buffering of the VCO output, but I don't see how it could be improved. http://www.mcarsweb.com/_divers/4VCO.jpg http://www.mcarsweb.com/_divers/5PLL.jpg I'm really getting mad with this problem ! So thanks to all of you who will answer ;-) |
Thank you Ashhar, your tip was the best :-) I've added a grounded gate FET
between the VCO and the PLL and now the receiver works as well with as without the PLL circuit. I still have to adjust the loop filter because it is not perfect; it can lock on the right frequency and keep it but the output voltage of the filter doesn't look clean enough on the scope. Thanks everybody for your advises, and cya ;-) Damien |
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