Hi all,

Firstly, does anyone bother designing with Y-parameters *at all* these
days?

Then... (talking of the common-emitter configuration in this case)
The only variable according to the Ebers-Moll transistor model apart
from the device-specific "Is" which has any effect on Ic is the
potental difference applied across the B/E junction. The signal
voltage thus applied is loaded by the resistance of this diode. At
DC., the loading is at a maximum and the entire PD appears across it.
Right so far? As the applied signal voltage increases in frequency,
the feedback capacitance (B-C) and the B-E junction capacitance form
an AC bypass path across the B/E resistance above-mentioned. The two
capacitances acting in concert shunt more and more of the applied
signal voltage to ground, bypassing the emitter diode resistance,
lowering the device input impedance and resulting in less and less
applied Vbe across this diode and consequently less and less Ic output
swing?

What I'm getting at is that Ebers-Moll is still good at RF, *provided*
one allows for the bypassing of the emitter diode's resistance by the
combination of Cb and Ce. Correct?
And CJC and CJE are the relevant Spice model parameters?

Thanks,

p.
--

"What is now proved was once only imagin'd." - William Blake, 1793.