Thanks for the answers.
I have one TCXO 40Mhz 1Vp-p 10K//15pf Clipped Sine Wave.
My idea is of:
1) to gain 40Mhz Sine Wave through buffer with resonant circuit come
to an agreement for 2nd the IF (40.455)
2) to gain 20Mhz with a divisor x2 for the 16F877
3) ..and last.. to gain before 120Mhz (40x3) and then 480Mhz with
helical filter for clock the AD9954.
Thoughts are possible? It is one bad solutions??
Thank you again.



ha scritto nel messaggio
...
The clipped sinewave is the simplest output for a TCXO, it's usually just
a
capacitor connected between the emitter of the oscillator and the output
pin.
You have to be careful what you connect to it, it's possible to throw the
temp
compensation out of tolerance. Most CMOS PLL chips have a reference
frequency
input that handles it well. If you're rolling your own PLL from SSI or MSI
chips, you probable want to build up a buffer to make the clipped sinewave
into
TTL or HCMOS levels, or pay extra for a TCXO with the needed circuit built
in.




On Sun, 17 Jul 2005 20:34:25 GMT, "Mario Bros" wrote:

Hi folks,
I would have to ask a clarification regard to the TCXO.
They are found with output TTL, HCMOS and CLIPPED SINE WAVE.
It is just with respect to this last type that I would want to have
elucidations on when it is convenient to employ it, which the advantages
and
the disadvantages and which the extension of spectral harmonicas.
In synthesis, from the plan point of view, which are the motivations that
they make to incline towards a Clipped oscillator?

Anticipated thanks.

73's de IK6GQC Rocco