In article ,
Dan writes:
On Sat, 14 Aug 2004 13:41:55 -0500, clifto wrote:

They were going to try that on computer memory a few years back, until
they became aware of how many computer support people were willing to
quit maintaining their ultra-important computers in protest. I figured
they'd try again during the 9/11 job slump, but maybe they realized that
the job market would rebound and their new slaves could quit in protest
then too. Had they succeeded, you'd find memory at $5 per megabyte today.

I remember when it was $400 per megabyte!

This is definitely not meant to be a 'I remember when' war, but with
normal chip technology, on S-100 (and/or QBus on LSI-11), I designed/built
memory cards for both, where the 16Kx1 chips (AFAIR) were $30/each and
the LSI-11 board contained 16 of the chips (the memory was 16k x 16bits)
that were effective 32kbytes. The cost for the 32kbytes was $480... I might
be off a little in cost, but the general cost range was correct. As I
was building the project, I seem to remember that the cost dropped from
$30/each down to approx $8. That is STILL incredibly expensive when
compared with today.

For example, the fastest cycle time for the commodity computer memory might
have been approx 250nsec, while main memory on an 866MHz RDRAM PC real world
speed was 170nsec latency in 1999, bypassing cache effects (all numbers
are approx) and a
3.2GHz DDR PIV might have 80nsec memory latency. (Latency vs. cycle isn't
the same
thing, but order of magnitude is probably similar in this case.) For
the old memory, the latency and bandwidth would be of similar order, but
for the new stuff, the bandwidth and latency are much more decoupled.

For example, current DDR might have a latency of 80nsec, but the bw
might be 3300Gbytes/sec. If the current memory wasn't so pipelined,
but maintained the latency of 80nsec, then the bandwidth would have
been a sluggish 12Mbytes/sec. Equvalently, an old DRAM might have
had a latency of 250nsec, but a bandwidth (of something more advanced
than the original 16kx1 chips) might be 8Mbytes/sec (well, not exactly,
but the concept is true.)

Current processors and computer systems are very dependent upon asynchronous
queued out of order operations in order to get their incredibly high
performance. (There are chips that can provide 5nsecs of latency, but
other tradeoffs cause architectural decisions that disfavor 5nsecs of
latency/cycle time for main computer memory on PCs.)

John