From: xpyttl on Jul 17, 5:56 pm

"Ian White G/GM3SEK" wrote in message
...

For something like a receiver tuning control, even 256 steps/rev would
sound 'jumpy'. However, you could gear it up mechanically so that even a

Actually, 256 is getting too high in most cases. The "jumpiness" comes from
the size of the step, i.e., the number of Hz per step. Encoders between 50
and 100 are probably the easiest to deal with. You generally want to make
the step size small, like 1 or 10 Hz, but you don't want hundreds of turns
to cover the band.

Ahem, have you guys agreed on what defines "jumpiness?" :-)

I'm into the actual receiver portion of a PLL-LO-controlled
HF SW BC receiver tuning in 1 KHz steps. The PLL and its
controlling circuitry are done and a 256-step Grayhill shaft
encoder is used with a shaft encoder decoder circuit from Dr.
Robert Dennis. That decoder circuit uses 3 HCMOS DIPs for
Up/Down counters having separate Up and Down clocks. One more
HCMOS DIP gate package is required for Up/Down counters having
a single clock input and having an Up or Down mode control pin.

At very high resolutions, the pulses can come very fast,
so it gets tricky to distinguish the closure from noise.

I didn't find it so. The Dennis Decoder will allow shaft
encoder rotation rates of 150 RPM with a 240-step shaft
encoder, no problem. Pressed faster, it can handle 300 RPM
or 5 revolutions per second...quite fast tuning. It is
easily comparable to the "old" tuning control on my Icom
IC-R70 which has an estimated 200 steps per revolution.

Of course,
higher counts can be made to work, and in principle, can be made to work
better. But generally, one is dealing with low level software and finite
compute resources to read the encoder, so the very high resolutions can
actually become somewhat problematic.

While the BCD Up/Down counter ICs are getting rather scarce,
it takes only three more packages to "see" three-decimal-digit
resolution. Add another IC for four-decimal-digit resolution.
4-stage binary Up/Down counters are still being made, no problem.

Ain't no software for this critter...it's all hardware. The
Up/Down counter drives the PLL divider directly (through a
EPROM translator, preprogrammed, or through some more logic
gates). Grayhill shaft encoder output is TTL/HCMOS level at
+5 VDC into the encoder. Very fast jumps in handling the
shaft encoder knob don't upset the counter chain.

If you want some nice decoder circuit schematics and a set of
decoder waveforms, let me know at signature address below and
I can attach the ZIP file (19 K) to e-mail.

If someone wants an Absolute position control, that could be
done with an additional optical sensor and track that resets
the Up/Down counter at all-zeroes. Not the same as a Gray
Code multiple track and sensor encoder with a collection of
Exclusive-Or gates to make it straight binary, but cheaper.

bit bit