Dana Myers K6JQ wrote in message ws.com...
R C wrote:
That is step 2 The target CPU will most likely be a Mega8535 AVR,
so conversion to integer is definately indicated.

Heh. You're tempting to cobble up the DDS code for giggles and
flash it into an atMega16 I have sitting here ;-)

Hmm.. shot one, for GCC, no ASM. Nominally targetted for 8515 at 8
mhz, easy
to redo.

Not quite finished implementing, and definately not tested, but
framework should be there.

R C
KG4MVB

-- begin fsk2.c --

#include avr/io.h
#include avr/pgmspace.h


// Generated via sine.c. Theory suggests you can use reflexive nature
of sine.
// but we'll keep it simple. Besides, we have 8K of flash.

// For avr use prog_uchar?
prog_uchar s_table[] = [
0x80,0x83,0x86,0x89,0x8C,0x90,0x93,0x96,0x99,0x9C, 0x9F,0xA2,0xA5,0xA8,0xAB,0xAE,
0xB1,0xB3,0xB6,0xB9,0xBC,0xBF,0xC1,0xC4,0xC7,0xC9, 0xCC,0xCE,0xD1,0xD3,0xD5,0xD8,
0xDA,0xDC,0xDE,0xE0,0xE2,0xE4,0xE6,0xE8,0xEA,0xEB, 0xED,0xEF,0xF0,0xF1,0xF3,0xF4,
0xF5,0xF6,0xF8,0xF9,0xFA,0xFA,0xFB,0xFC,0xFD,0xFD, 0xFE,0xFE,0xFE,0xFF,0xFF,0xFF,
0xFF,0xFF,0xFF,0xFF,0xFE,0xFE,0xFE,0xFD,0xFD,0xFC, 0xFB,0xFA,0xFA,0xF9,0xF8,0xF6,
0xF5,0xF4,0xF3,0xF1,0xF0,0xEF,0xED,0xEB,0xEA,0xE8, 0xE6,0xE4,0xE2,0xE0,0xDE,0xDC,
0xDA,0xD8,0xD5,0xD3,0xD1,0xCE,0xCC,0xC9,0xC7,0xC4, 0xC1,0xBF,0xBC,0xB9,0xB6,0xB3,
0xB1,0xAE,0xAB,0xA8,0xA5,0xA2,0x9F,0x9C,0x99,0x96, 0x93,0x90,0x8C,0x89,0x86,0x83,
0x80,0x7D,0x7A,0x77,0x74,0x70,0x6D,0x6A,0x67,0x64, 0x61,0x5E,0x5B,0x58,0x55,0x52,
0x4F,0x4D,0x4A,0x47,0x44,0x41,0x3F,0x3C,0x39,0x37, 0x34,0x32,0x2F,0x2D,0x2B,0x28,
0x26,0x24,0x22,0x20,0x1E,0x1C,0x1A,0x18,0x16,0x15, 0x13,0x11,0x10,0x0F,0x0D,0x0C,
0x0B,0x0A,0x08,0x07,0x06,0x06,0x05,0x04,0x03,0x03, 0x02,0x02,0x02,0x01,0x01,0x01,
0x01,0x01,0x01,0x01,0x02,0x02,0x02,0x03,0x03,0x04, 0x05,0x06,0x06,0x07,0x08,0x0A,
0x0B,0x0C,0x0D,0x0F,0x10,0x11,0x13,0x15,0x16,0x18, 0x1A,0x1C,0x1E,0x20,0x22,0x24,
0x26,0x28,0x2B,0x2D,0x2F,0x32,0x34,0x37,0x39,0x3C, 0x3F,0x41,0x44,0x47,0x4A,0x4D,
0x4F,0x52,0x55,0x58,0x5B,0x5E,0x61,0x64,0x67,0x6A, 0x6D,0x70,0x74,0x77,0x7A,0x7D
];


// Hmm.. for now assume an 8515-class running at 8 mhz. I've got a few
// spares in the box, and haven't gotten to ordering the megas from
digikey
// yet.

// This will not be a dedicated DDS, and it only needs to produce two
// frequencies. Output methods include a DAC (R2R or separate), I2C
digipot
// (not sure if fast enough, but have some laying around) or PWM.
Assume DAC
// for now.


// Choose an apropriate sample rate. ~10 khz should be adequate, and
not put
// a large burden on the AVR. A low pass may be indicated.

// Keep things simple.. use 32-bit accumulator, so we can run on a
slow clock.
// This is overkill, but easier to do in GCC than 24-bit.
volatile register uint32_t accum, freq_offset;

/* May want to make a circular buffer */
volatile uint8_t fsk_out, fsk_bit, fsk_done_flag;


// Okay.. 8M clock

// Use /256 for TCNT0. 3 of the /256 cycles will give us a sample rate
of
// 10416 Hz
#define TCNT0_PRESCALE 4
#define TCNT0_PERIOD 3


// FCLK = 10416/2^32 = 2.43x10^-6 resolution.
// 1199.9999987893 hz
#define MARK 494780232
// 2200.0000002057 hz
#define SPACE 907097093

// Use /8 for TCNT1. This puts our nominal bitrate at 1199.4 bps,
prolly close
// enough. (0.05%)
#define TCNT1_PRESCALE 2
#define BIT_PERIOD 667

SIGNAL(SIG_OUTPUT_COMPARE0)
{
// Not sure how well this will be optimized, but as it's only run
// every 10khz..
accum += freq_offset;
PORTC = PRG_RDB(s_table + (accum 24));
0CR0 += TCNT0_PERIOD;
// is this needed?
sei();
}


/* This needs to be set pretty close to 1/1500 second. */
SIGNAL(SIG_OUTPUT_COMPARE1A)
{
switch (fsk_bit)
{
case 0 : freq_offset = MARK; break;
case 9 : freq_offset = SPACE; fsk_done = 1; break;
default : freq_offset = (fsk_out (fsk_bit-1)) ?
MARK : SPACE; break;
}
fsk_bit++;
// If only item on TCNT1;
//TCNT1 = 0;
// If sharing TCNT1
OCR1A += BIT_PERIOD;
// is this needed?
sei();
}

void main (void)
{
//setup everything, add ax.25 framing and HDLC encoding. optimized
//crc16 in avr-libc.
}