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Input stage for VHF frequency counter in an FPGA?
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February 23rd 06, 03:14 PM posted to sci.electronics.design,comp.arch.fpga,rec.radio.amateur.homebrew
Spehro Pefhany
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Input stage for VHF frequency counter in an FPGA?
On 23 Feb 2006 06:49:32 -0800, the renowned
wrote:
Jan Panteltje wrote:
Just a partial reply... I think 7400 series should stop way below 200mHz,
perhaps 50MHz?
It's either a 74AC04 or possibly a 74HC04 (it's upside down so I can't
tell) and it's self oscillating at 294 mhz - (it's stable enough for
the counter to read... a fast scope shows it approximately as a
sinewave.
It seems to be oscillating at about 1/tpd... can't even really pull it
much with finger capacitance - only about 10 mhz.
Interestingly, if I short a the floating input-output pair of an unused
inverter with the scope probe, that runs a bit slower around 260 mhz...
wheras the gate in use has about 20k of resistance in the feedback
path.
I would make a small diff amplifier, did something 40 years ago (yes 40!)
with I think it was BFY90 transistors, then invert with 2 more and drive
the LVDS input.
I may give your transistor circuit a try, either with components or
simulation, thanks.
What about using a stand-alone LVDS receiver? Eg. Pericom
PI90LV179W.
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