RadioBanter - View Single Post - Input stage for VHF frequency counter in an FPGA?

wrote:
The other day I found myself needing a short gate time ~200 mhz
frequency counter for an automated test, and since I had an FPGA board
on hand I whipped one up quickly. Getting it reading and reporting to
my computer was the easy part.

Ah, the input stage....

I've got about 4dBm of RF into 50 ohms to play with - about a volt p-p
or a little more if it's high-Z. The output of the device under test
has a transformer and then a series cap to create an unbalanced output.

I did something ugly with a 3.3v cmos 7406 varient and a feedback
resistor, which works well enough to get an accurate reading on one
version of the device under test, but not on the other (both have been
verified with real test equipment) It also tends to self-oscillate
with no input...

I'm surprised any CMOS 7406 variant really goes to 200MHz! I think you
got lucky with the one that did work.

What would be the right way to do this using on hand parts, such as
abused logic, little 1:1 or 2:1 RF transformers, etc?

I like high-speed comparators (often called "differential receivers" or
"LVDS receivers" on the spec sheet) for this.

One idea is to
use another gate with a feedback resistor and cap to ground in the hope
of establishing the threshold level, and then using a transformer to
swing another input above and below this. Most parts on hand are SMD -
which means dead bug construction in SOIC scale under the maginifier -
discourages extensive experimentation.

The nice thing about differential receivers a

1. Easy to set the comparison level.
2. Lowish input impedance but not too low, such that you set the
impedance by putting a 50 or 100 or whatever ohm resistor there.
3. At least for the non-LVDS parts, there's only one or two receivers
per package so even when it's not SMD it's easy to do dead-bug
prototyping.
4. They already have some semblance of defined open-circuit response
(usually called "fail-safe" for some bizarre reason in the spec sheets)
to prevent oscillating.

Why do most abuse-of-logic RF applications seem to use NAND gates
rather than inverters? From a digital perspective NAND gates are a
universal element, but once you tie their inputs together, is there
something to be gained from having two inputs in parallel?

Usually the hex inverter packages cost a little bit more than the
4xNAND gate packages. It's nice to have the extra input to act as an
enable etc. And once you start running these parts into the linear
region you probably do not really trust using the other sections for
other functions.

Is there a way to use a differential input configuration on an FPGA to
input a balanced RF signal directly? Theoretically this should be an
FPGA clock input... The device in use currently is an Altera Stratix
II, but a Xilinx S3 kit is available.

You can even feed in non-balanced RF subject to some limitations.

If ordering things, what would be a good default low supply voltage
HF/VHF gain component to have on hand? I seem to recall lots of
last-millenium ham designs using the MC1350P video IF amp, but what
would make sense today?

VHF? MMIC's, at least as long as you have only need for AC coupling.

Tim.