RadioBanter - View Single Post - Input stage for VHF frequency counter in an FPGA?

wrote:

Jan Panteltje wrote:

Just a partial reply... I think 7400 series should stop way below 200mHz,
perhaps 50MHz?

It's either a 74AC04 or possibly a 74HC04 (it's upside down so I can't
tell) and it's self oscillating at 294 mhz - (it's stable enough for
the counter to read... a fast scope shows it approximately as a
sinewave.

It seems to be oscillating at about 1/tpd... can't even really pull it
much with finger capacitance - only about 10 mhz.

Interestingly, if I short a the floating input-output pair of an unused
inverter with the scope probe, that runs a bit slower around 260 mhz...
wheras the gate in use has about 20k of resistance in the feedback
path.

I would make a small diff amplifier, did something 40 years ago (yes 40!)
with I think it was BFY90 transistors, then invert with 2 more and drive
the LVDS input.

I may give your transistor circuit a try, either with components or
simulation, thanks.

There are some newer low voltage CMOS gates that are much faster than AC
series, I think they are called LVC and a few other names depending on the
manufacturer. The really fast ones don't support 5V supply operation
because they are made on a fine geometry process. This also makes them
faster. It would be very hard to stop it from self oscillating with no
input signal. In order to have a meaningful way of determining if you have
satisfied this requirement for not self-oscillating, you would first have
to define what is the minimum input amplitude that you expect it to be able
to accept and produce an output with reasonable duty cycle etc. Another
approach would be to make an input buffer that does self oscillate and make
a separate detector that measures the input signal amplitude and disables
the measurement when the input amplitude is below a certain threshold.

Chris

Chris