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Old February 24th 06, 04:12 AM posted to sci.electronics.design,comp.arch.fpga,rec.radio.amateur.homebrew
John Larkin
 
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Default Input stage for VHF frequency counter in an FPGA?

On Thu, 23 Feb 2006 16:23:13 +1300, Jim Granville
wrote:

wrote:
The other day I found myself needing a short gate time ~200 mhz
frequency counter for an automated test, and since I had an FPGA board
on hand I whipped one up quickly. Getting it reading and reporting to
my computer was the easy part.

Ah, the input stage....


Does the FPGA have LVDS option inputs ?
If it is new enough to have those, they are differential
amplifiers, designed for current mode signals, and will work
with thresholds 1V.
IIRC the LVDS spec has +100mV and -100mV levels.
Normally, they need a common mode bias of just over 1V, and the
better ones will also tolerate rail-rail drive (on ONE ip),
but at reduced speed specs.
-jg


Second that. We've tested the Xilinx Spartan3 LVDS inputs and they are
excellent, super-fast comparators.

John