Andrea Baldoni wrote:

.....................................


The AGC line is derived from a fixed voltage using a 9V zener, then the RF
GAIN pot permit to divide this voltage from 100% to ground and feed it
(trough a resistor) to the first RF amplifier of the HF receiver (a DG
FET) as well as the first RF amplifier of the 2m converter, and the same
for 6m converter. It is also fed to the last but one CA3053. Other
amplifiers are fixed gain I suppose.
Everything in the receiver needs to reduce gain, lower this voltage by
more or less shorting it to ground.
For instance, the standby button shorts it to ground, silencing the
receiver completely. The RF level at the last IF instead reduce it by
means of common emitter transistor: the AGC voltage from zener at the
collector and the rectified and filtered IF at the base.
When you disable AGC, you disconnect the collector of this transistor,
thus the signal is let alone to the level adjusted with RF gain pot
(normally at maximum, so it is 9V).

Ciao,
AB

Ok, have you checked the Dual Gate FET to insure that the bias supplied by
the RF gain control puts the device at maximum gain when the AGC is off?

Dual Gate FET's have transducer gain curves that are peaked curves.
Depending upon the Gate 2 voltage, the transducer gain can actually go down
as the Gate1 to Source voltage goes up.

I would still be interested in knowing *exactly* what the AGC voltage on the
gate of the DGFET is for 1) AGC on, no signal, RF gain wide open, and 2)
AGC off, no signal, RF gain wide open. It would also be interesting to know
what the Gate 1 bias voltage is for each state as well.

I'll bet you'll find an interesting interaction between the bias voltages
and the actual stage gain as the controls are manipulated.

tim ab0wr