If you get this twice, blame it on the strange behaviour of the
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On Apr 16, 8:18 am, Cecil Moore wrote:
Keith Dysart wrote:
So, out of curiosity, what do you think the outcome of my
experiment would be?
With an IC-706? I don't know. Others have tried it with
varying results.
Do 10 cent resistors ever work? Or is a circulator always needed
to prevent re-reflections?
Your 10 cent resistor can be thought of as a low dB
pad of sorts. It will attenuate but not eliminate
re-reflection.
Remembering that this conversation was about realizing mistakes,
it would be highly valuable if you were to 'realize' that you
are in error about this. If the generator output impedance is the
same as the characteristic impedance of the line, then a wave
incident upon the generator is not reflected at all. Zero.
With regards to Icom equipment, there is no dispute of the above
fact, but rather, there is dispute about whether the output
impedance of the transmitter can be characterized.
Leaving transmitters aside, it is easy to characterize the output
impedance of a generator constructed as a voltage source in
series with a resistor. The output impedance is the value of
the resistor.
Again, let me remind you of Ramo &
Whinnery's warning not to attach importance to
what is calculated to happen inside an equivalent
source.
Ramo and Whinnery's warning must be taken seriously but applies
only with reference to an equivalent circuit. If the actual
circuit is as described, then the caution does not apply.
There are models available for virtually
any amplifier you might choose but I don't know
how those models handle reflections.
It is well understood in all the literature how the generator
described above handles reflections. If the output impedance
is the same as the characteristic impedance, then there is
no reflection.
This follows from the superposition principle and its application
to generators. You have indicated some reluctance to accept this,
but I get the feeling you are more convinced by measurement than
by theory. So I propose we continue with the experiment so that
you can 'realize' that for linear generators, superposition does
apply and there is no reflection from a generator whose output
impedance is the same as the characteristic impedance of the line.
But we need an experiment. I have a slightly better one than
previously described that you can easily replicate to convince
yourself. This way you do not need to take my word for the results.
Begin by creating two files in the same directory with the content
included below my signature.
Then download and install LTspice from Linear Technology:
http://www.linear.com/designtools/so...witchercad.jsp
Double click on "TLsuperposition.asc", one of the files previously
created.
You will see a schematic with 3 transmission lines.
The top transmission line, 'bidirectional', has two generators
attached to it; one on the left and one on the right. The TL
has a 50 Ohm characteristic impedance and the two generators
have 50 Ohm output impedances, easily seen from the schematic.
The source in the left generator creates a 5 V, 2 MHz sine
wave. The source in the right generator creates a 7 V, 3 MHz
sine wave. Thus two waves are sent towards each other across
the transmission line.
The second transmission line is connected to a similar generator
on the left but is terminated by a resistor on the right.
The third transmission line is connected to a similar generator
on the right and terminated by a resistor on the left.
If superposition holds, the observed signals at the two ends
of the 'bidirectional' line will be sums of the signals at the
corresponding ends of the 'left-to-right' and 'right-to-left'
line.
So click Run to get some observations. Some traces appear.
The first 10 microseconds are recorded and displayed.
The top pane shows the outputs of the left and right sources.
The middle pane shows the signals at the left and right ends
of the bidirectional transmission line as well as the sum
of the signals at the left end of the l-to-r and r-to-l lines,
and the sum of the signals at the right end of the l-to-r
and r-to-l lines. Since some of these traces are on top of
each other, click on the signal name to bring the desired
trace to the top. They are on top of each other because
they have the same values, as expected.
The third pane shows the difference between the left end of
the bidirectional line and the sum of the left end of the other
two lines, and the same for the right. Note that the maximum
difference is around 500 nanovolts. This is not bad. Theory
says it should be zero, but given the limitations of simulation
500 nV is close enough. If this experiment were conducted with
real parts, it would be impossible to get that close.
So we have run an experiment that demonstrates the results I
expected, but results that are not consistent with your
contention. So I claim superposition holds at generators as
well as loads. Reflections do not occur even when the source
is energized.
You may like to experiment. Try different frequencies. Try
different waveshapes. Try a different length of line. Try
different source and terminating resistors. (Just remember
that you have to change the appropriate items on both the
bidirectional line and the other two for the sums to be
correct).
So what is the probability that you now 'realize' you were
wrong and '10 cent' resistors actually do eliminate reflections.
I can not emphasize enough how important this result is to
you. It will allow you to use superposition to analyze the
behaviour at the generator end and a whole class of problems
which you could not previously solve will now be solvable.
....Keith
PS - Any questions? Just ask
---- Place the following data into "TLsuperposition.asc"
Version 4
SHEET 1 1276 756
WIRE -464 96 -512 96
WIRE 544 96 496 96
WIRE -336 112 -352 112
WIRE -112 112 -128 112
WIRE 128 112 112 112
WIRE 352 112 336 112
WIRE -464 144 -464 96
WIRE -352 144 -352 112
WIRE -352 144 -464 144
WIRE -256 144 -352 144
WIRE -128 144 -128 112
WIRE -128 144 -176 144
WIRE -16 144 -128 144
WIRE 112 144 112 112
WIRE 112 144 80 144
WIRE 224 144 112 144
WIRE 336 144 336 112
WIRE 336 144 304 144
WIRE 496 144 496 96
WIRE 496 144 336 144
WIRE -16 176 -512 176
WIRE 544 176 80 176
WIRE -512 192 -512 176
WIRE 544 192 544 176
WIRE -464 224 -512 224
WIRE -112 240 -128 240
WIRE 128 240 112 240
WIRE -464 272 -464 224
WIRE -256 272 -464 272
WIRE -128 272 -128 240
WIRE -128 272 -176 272
WIRE -16 272 -128 272
WIRE 112 272 112 240
WIRE 112 272 80 272
WIRE 224 272 112 272
WIRE 336 272 304 272
WIRE -16 304 -512 304
WIRE 336 304 336 272
WIRE 336 304 80 304
WIRE -512 320 -512 304
WIRE 336 320 336 304
WIRE 544 352 496 352
WIRE -112 368 -128 368
WIRE 128 368 112 368
WIRE -256 400 -288 400
WIRE -128 400 -128 368
WIRE -128 400 -176 400
WIRE -16 400 -128 400
WIRE 112 400 112 368
WIRE 112 400 80 400
WIRE 224 400 112 400
WIRE 496 400 496 352
WIRE 496 400 304 400
WIRE -288 432 -288 400
WIRE -16 432 -288 432
WIRE 544 432 80 432
WIRE -288 448 -288 432
WIRE 544 448 544 432
FLAG -512 192 0
FLAG -112 112 Vleft
FLAG 128 112 Vright
FLAG 352 112 VsrcR
FLAG -336 112 VsrcL
FLAG -288 448 0
FLAG -112 368 VloadR
FLAG -112 240 VgenL
FLAG 128 240 VloadL
FLAG 544 192 0
FLAG 336 320 0
FLAG 544 448 0
FLAG -512 320 0
FLAG 128 368 VgenR
SYMBOL voltage -512 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 35 41 Left 0
WINDOW 3 24 115 Left 0
SYMATTR InstName VbidirL
SYMATTR Value SINE(0 5 2e6)
SYMBOL voltage 544 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 36 55 Left 0
WINDOW 3 9 99 Left 0
SYMATTR InstName VbidirR
SYMATTR Value SINE(0 7 3e6)
SYMBOL tline 32 160 R0
WINDOW 0 -32 -35 Left 0
WINDOW 3 -78 34 Left 0
SYMATTR InstName Tbidir
SYMATTR Value Td=1.1e-6 Z0=50
SYMBOL res 320 128 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 19 86 VTop 0
SYMATTR InstName Rright
SYMATTR Value 50
SYMBOL res -272 160 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 11 28 VBottom 0
SYMATTR InstName Rleft
SYMATTR Value 50
SYMBOL tline 32 288 R0
WINDOW 0 -23 -34 Left 0
WINDOW 3 -95 35 Left 0
SYMATTR InstName Tltor
SYMATTR Value Td=1.1e-6 Z0=50
SYMBOL tline 32 416 M0
WINDOW 0 -25 -36 Left 0
WINDOW 3 -92 38 Left 0
SYMATTR InstName Trtol
SYMATTR Value Td=1.1e-6 Z0=50
SYMBOL res -272 288 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 12 26 VBottom 0
SYMATTR InstName RgenL
SYMATTR Value 50
SYMBOL res 320 384 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 18 86 VTop 0
SYMATTR InstName RgenR
SYMATTR Value 50
SYMBOL res 208 288 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 12 25 VBottom 0
SYMATTR InstName RloadL
SYMATTR Value 50
SYMBOL res -160 384 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 19 83 VTop 0
SYMATTR InstName RloadR
SYMATTR Value 50
SYMBOL voltage 544 336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 36 55 Left 0
WINDOW 3 7 99 Left 0
SYMATTR InstName VsrcR
SYMATTR Value SINE(0 7 3e6)
SYMBOL voltage -512 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 35 41 Left 0
WINDOW 3 24 115 Left 0
SYMATTR InstName VsrcL
SYMATTR Value SINE(0 5 2e6)
TEXT -496 416 Left 0 !.tran 10e-6
---- The above line was the last one to go into "TLsuperposition.asc"
---- Place the following data into "TLsuperposition.plt"
[Transient Analysis]
{
Npanes: 3
Active Pane: 2
{
traces: 2 {524296,0,"V(vleft)-(V(vgenl)+V(vloadr))"}
{524294,0,"V(vright)-(V(vgenr)+V(vloadl))"}
X: ('µ',0,0,1e-006,1e-005)
Y[0]: ('n',0,-5.4e-007,9e-008,4.5e-007)
Y[1]: ('_',0,1e+308,0,-1e+308)
Volts: ('n',0,0,0,-5.4e-007,9e-008,4.5e-007)
Log: 0 0 0
},
{
traces: 4 {268959756,0,"V(vleft)"} {268959751,0,"V(vright)"}
{524291,0,"V(vgenl)+V(vloadr)"} {524292,0,"V(vgenr)+V(vloadl)"}
X: ('µ',0,0,1e-006,1e-005)
Y[0]: (' ',0,-6,1,6)
Y[1]: ('n',0,1e+308,2e-009,-1e+308)
Volts: (' ',0,0,0,-6,1,6)
Log: 0 0 0
},
{
traces: 2 {524293,0,"V(vsrcl)"} {524290,0,"V(vsrcr)"}
X: ('µ',0,0,1e-006,1e-005)
Y[0]: (' ',0,-7,1,7)
Y[1]: ('_',0,1e+308,0,-1e+308)
Volts: (' ',0,0,0,-7,1,7)
Log: 0 0 0
}
}
---- The above line was the last one to go into "TLsuperposition.plt"
Now what is the chance that this makes it all through without
any carriage return and line feed issues? I suppose I get to try
when it comes back.