On Sat, 30 Jun 2007 16:57:19 -0700, john wrote:

I'm trying to get an idea of some of the tradeoffs involved in
determining
where to perform the analog to digital conversion for a SDR design
which
uses 200 MHz as the first IF (pick due to SAW filter availability and
it's
high enough to simplify the front end filter bank ... the receiver is
a
homebrew type intended to cover .5 - 600 MHz with a maximum signal
bandwidth of 200 kHz).

Some options:

1) Sample at the first IF using subsampling.

Advantages: Eliminates the need for an additional LO and mixer.

Disadvatages: Brad Evans points out in a comp.dsp article entitled
"Undersampling (was: RF/IF digital receiver)" that using a high IF
means that it will be more sensitive jitter in the ADC clock.

The LTC2203 does 25 Msps with a 16 bit output and has a front end
which
can handle 380 MHz.

The AD7763 does 40 Msps with a 24 bit output and includes a digital
FIR.
However, it's not clear to me what's the maximum frequency that it
can handle.
What's very interesting is that Analog Devices has an evaluation
kit
(EVAL-AD7763) available from Digikey for only 163 dollars and it
includes (according to the literature) a BF537 EZ-KIT Lite. This
appears
to be a very inexpensive way to experiment with SDR.

2) Convert the first IF to a second IF of 21.4 MHz and then subsample.

-- snip --

3) Convert the second IF to a third IF of 2.9 MHz and sample using a
AD9874.

-- snip --

I think you may be overdoing your concern on the sampling clock. The
jitter that matters is the amount of time jitter on the clock. If you can
generate a tone that's pure enough to down-convert the 1st IF, then you can
generate a clock that's pure enough to down-sample. In either case, if
you're crystal controlled you'll probably be much more stable than the LO
with which you're doing your first conversion.

At this point you need to ask not can you _generate_ a time base that's
low enough jitter to do good sampling, but can you _preserve_ the clean
signal through your entire sampling path, starting with whatever logic
generates the clock, all the way through to the actual sampling. If the
sampling takes place inside the ADC then you need to hope (or verify from
the data sheet) that the ADC isn't introducing much jitter. If you're
really concerned about this then you could make your own sampler with
appropriate components to insure the jitter is within your control.

--
Tim Wescott
Control systems and communications consulting
http://www.wescottdesign.com

Need to learn how to apply control theory in your embedded system?
"Applied Control Theory for Embedded Systems" by Tim Wescott
Elsevier/Newnes, http://www.wescottdesign.com/actfes/actfes.html