View Single Post
  #5   Report Post  
Old July 5th 03, 10:40 AM
Richard Hosking
 
Posts: n/a
Default

Check http://www.qsl.net/ke5fx/synth.html
for a 1-2 GHz design using DDS/PLL technology

wrote in message
...

Typically the DDS is used as the reference oscillator for the PLL,

resulting
in the VCO being at a multiple of the DDS output frequency. The idea

being
that the VCO output will have decent phase noise performance with the

fine
frequency resolution of the DDS, and resaonably fast stepping

times---"the
best of both worlds", you might say.

I discovered an interesting alternative at :
http://lea.hamradio.si/~s57nan/ham_r.../dds_9851.html



This idea has the DDS acting as a programmable divider inside the PLL
feedback loop. Ok, what are the advantages or disadvantages of doing

this?

At the frequencies we used it would have been necessary to use a prescaler
in front of the DDS. The newer chips seem to be getting up towards a 1GHz
clock rate, so this might be an option

What does it do to the phase noise and lock-up time? And what about the
spurs?


Spurious are down to normal analogue pll levels.


We found in our design that phase noise was attenuated by the loop inside
the loop bandwidth, but was dependent on the quality of the VCO outside
this. The PLL is sensitive to any spurs on its reference and multiplies them
by 20 Log N dB, where N is the loop division ratio. This applies near the
comparison freq and at harmonics of the comparison freq. So you have to
severely band limit the output of the DDS. If it were in a loop with a
constant reference freq output, you could get even better band limiting, so
this problem might be reduced. Alternatively, the loop filter would get rid
of wideband spurs. Another advantage would be that the computation of output
frequency would be somewhat simpler than with the other appraoch

Does anyone have a pointer to a detailed analysis of this approach?

Richard


As is phase noise.

Lock-up time is somewhat slower than the DDS, this is reduced down to

normal PLL
times as well.

Doing it this way gives you one advantage over a normal analogue pll -

small
frequency steps ( = normal analogue pll with fractional divider).

Clive