On Tue, 22 Jul 2003 11:44:07 +0000, W3JDR wrote:

Anyone know of a PIC-based frequency locked loop for VFO control? I'm
looking for something that can be programmed with a frequency word, and then
it aquires and maintains the frequency. I've seen frequency 'stabilizers'
but most of them just hold the frequency once it's been manually set. There
are also PIC-assisted DDS designs, but these are more complex thatn I want,
use more power then I'd like, and are not as clean as a simple voltage
controlled oscillator.

Mine is at http://homepage.eircom.net/~ei9gq/stab.html
Have a look at Hans Summers and Richard Hoskings web-pages.

It seems to me that the PIC should be able to measure the frequency,
determine the error, and operate a very simple charge-pump/VCO to put the
frequency where it wants.

Joe
W3JDR


What you are describing is a conventional PLL. PIC based
stabilisers or 'frequency locked loops' usually have very
long gate times for counting the frequency and a fairly
narrow frequency control range. My circuit uses a 100mS
gate time and a control range of +/- a couple of KHz.

If you want to cover a larger frequency range with your
VCO, you will need to use a much shorter gate time to
keep tight control of the VCO frequency. This will
increase the tuning steps and will also increase the
phase noise on the VCO output. You soon run into the
the same trade offs and compromises that you get with
any PLL design.

A PLL/DDS combination seems to be the best way to
go. I recently built a 21MHz VFO for a 10M transceiver.
The 21MHz VCO is mixed with the output from a 17MHz
crystal oscillator. The resulting 4MHz signal is
phase locked with a 4MHz signal from an AD9835 DDS
chip. The DDS is controlled by a PIC16F84. I use the
10M rig to drive a homebrew transverter for 144MHz.
I am delighted with the results. The RX is free from
the usual birdies you get with a DDS VFO. The phase
noise is low enough that I can operate within a few
KHz of some very strong local stations on 2M SSB.

73, Ed. EI9GQ.


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