This is an intriguing discussion
The problem with a FLL will be as Joe and Ed say - that to get reasonable resolution in a FLL , you have to count a lot of pulses and this takes a while. You are comparing one count to the next - ie one count is equivalent to the reference, while the next count is equivalent to the VCO signal. In my design (which is based on Ed's originally) the gate time is 100msec, which means the comparison freq and therefore resolution is about 10 Hz, and therefore the lockup time is pretty slow. I presume it would be possible to have the loop capture lock, but I have not explored this. The loop filter would have to be carefuly designed and I suspect lockup time would be pretty long. I think a better idea would be as Joe says to have the coarse resolution set by a DAC and a coarse tuning varicap without any loop. The fine resolution could then be set by a second freq locked system with a swing of say 5 KHz as in our current system. You would have to have a voltage tunable VFO which means phase noise might not be so good.

I have been thinking about an alternative for HF, which is somewhat more complex, but should give excellent phase noise performance. I would use a microwave synthesizer usin DDS/PLL techniques for say 1000-1500 MHz
See http://www.qsl.net/ke5fx/synth.html for a suitable design. This could then be fed to a programmable divider - a second LMX2326 could be used with the main divider output being the output of the synth. The rest of the second PLL chip (reference divider/phase comparator etc) would not be used. The programmable divider is set to give an output anywhere in the HF (or VHF for that matter) spectrum as desired. The phase noise performance of this synth at microwaves is in the order of -90dBc/Hz at 10KHz offset.Dividing it from say 1200 MHz to 30 MHz would improve this by 20log N where N is the division ratio to give phase noise of better than -130 dBc/Hz at 10 KHz offset, with almost infinite resolution and digital settability. The only downside is computational overhead for the processor, but this shouldnt be a problem with modern micros. Current drain could be reduced over the current design when the new AD DDS chips become available (AD9951 etc)
Anyone have any comments?

Richard


W3JDR wrote in message ...
Ed,

You said:

If you want to cover a larger frequency range with your
VCO, you will need to use a much shorter gate time to
keep tight control of the VCO frequency. This will
increase the tuning steps and will also increase the
phase noise on the VCO output. You soon run into the
the same trade offs and compromises that you get with
any PLL design.


I don't completely agree. there are several ways to skin this cat. One might be to implement a simple R-2R D-A converter in the PIC to do coarse frequency tuning according to a lookup table, and let the 'huff & puff' stabilizer do the fine corrections. No different than manually setting the tuning capacitor on the VFO and then enabling the stabilizer.

Having said that, there are PIC firmware designs that implement a 40+ MHz counter with 10hz resolution and 100 msec count interval. Combine this with a simple charge pump, and I don't see an FLL with any worse performance than a hardware PLL. Admittedly it's not as good as a DDS for resolution/speed, but it might have advantages for simplicity, power consumption, spectral purity and cost.

Bottom line is, I know most of the other ways to generate a clean & stable programmable RF source. What I wanted to find out is if anyone had done it with a PIC and little else. You came close with your stabilizer, but it can only stabilize, not acquire.

Joe