Damien
There are two main possibilities (and a few others as John Miles says)
First the 187 KHz could be a reference spur if that is the comparison
frequency. I note you are using a 10.24 MHz clock. What is the R (reference
divider) ratio and main N ratio? These will be entered by software or
hardwiring/switching various pins. If the signal is a reference spur than it
could be attenuated by an additional pole (RC network) before the VCO
A single RC pole will attenuate at 6dB/octave above its corner (3dB) freq,
so to get any sort of attenuation, the pole will have to set at about 1/10
of the unwanted signal/reference (say 20 KHz) or lower.

Alternatively the signal could mean the loop is unstable, in which case you
might have to go back to design basics
How did you arrive at the values for the loop filter?

Richard

Damien Teney wrote in message
...
Hello all,
I've already done a post a few days ago about a PLL system I had build.
The
initial problem was almost solved, but it isn't yet perfect.
In fact I made a PLL with a MC145152 IC, that I added to an existing VCO
(see

http://www.mcarsweb.com/_divers/sche...cation-note_98)
. It works quite well but the output signal, that is fed into the VCO, is
varying a bit at a frequency of about 187 KHz
(http://www.mcarsweb.com/_divers/oscillo.jpg the vertical
scale is enlarged). I don't know if I should adjust the filter values, or
add a additional small
filter just before the VCO (with a resistor and a capacitor between the
output and the ground).

What do you think about that ?

Thanks in advance for your answers ;-)


Damien