On Feb 20, 2:44*pm, "amdx" wrote:
"John Larkin" wrote in message

...



On Sun, 20 Feb 2011 09:20:12 -0600, "amdx" wrote:

Hi all,
I finished the amp that had the 5 Ghz transistor, I changed it to a
slower
one.
The objective of this amp is to cause minimal loading of the circuit it
is
measuring.
When I install the box cover the voltage gain drops by 7%, so I think the
input capacitor
plate is being loaded by the cover.
The input capacitor plates can be seen here;

http://i395.photobucket.com/albums/p...mspaced5mm.jpg

The plates are 1 cm x 1 cm spaced 5 mm apart.

I have thoughts about *rectangular plates 0.25 cm x 4 cm to get more
distance from the top cover, (and the bottom.)
Or a real gimmick cap where I twist a couple of 39 Gauge wires together
and
attach opposite ends to input and output.

*Any ideas to minimize input capacitance to the box?

Here's the amp in box.
http://i395.photobucket.com/albums/p...erampinbox.jpg

This is the original circuit page with schematic;
http://www.crystal-radio.eu/enfetamp.htm
* * * * * * * Thanks, Mike

PS, I was having trouble getting some close-up pictures, I grabbed a
magnifying glass and took some
pictures through that, works good.

Use a real surface-mount 0.3 pF cap, or a homemade coaxial cap. The 1
cm square plates are too big and have their own capacitance to the
world.

Bootstrap the drain of Q1.

"T" means transformer, which shows that this circuit was done by an
amateur. All that tricky stuff could be replaced by one opamp.

It could have close to zero Cin with a little positive feedback.

John

* * Bootstrap the drain of Q1.
You need to walk me through that, (I'm an amateur)

Ah, he's done some nice work on the subject of crystal radios and high Q
inductors.http://www.crystal-radio.eu/index.html
Page down to experiment with LC circuits.

* It could have close to zero Cin with a little positive feedback.

*How much closer? If the input cap is 0.3pf what do you the input impedance
is?
Input is 0.3pf, 20 Meg to ground driving FET gate.
* * * * * * * * * * * * * * * * * Thanks, Mikek

We're talking about something roughly like this:

+12V -o-----o-----------.
| | |
| | |
| | R5 3.3M
| |Q2 |
| \| | V1
| |---o-----o ~~ ~=+3V
| .| | |
| | | R6 1M
R3 | | |
C1 | | |C3 ===
10pF | g |-'d ---
in--||--o--|--| ---
| | |-.s |100n
R1 10M | |Q1 |
| | | |
o--o-||--o-----o-----------out
| C2 |
R2 10M 100nF|
| |
=== R4 470 R
|
|
===

C2 drives the center of the input bias resistor, which cancels the
loading caused by R1-R2. This is called "bootstrapping".

Q2 does the same thing for the drain terminal--it causes the drain
terminal to go up and down with the input signal. That saves the
input signal from having to charge Q1's gate-to-drain capacitance,
effectively making that capacitance disappear.

This front-end has *much* higher impedance than the original, and a
predictable gain that's close to 1.

R3 is to bias the FET output to (V1)/2, for maximum dynamic range.
Higher V1 would give bigger dynamic range.

A cheapskate could put a resistor in Q2's collector and use it as a
voltage-gain stage too.


--
Cheers,
James Arthur