On Wed, 18 Feb 2004 09:17:11 GMT, (Mike W) wrote:

I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave
to use as a timebase.

I have a 10Mhz IQD frequency standard of suitable accuracy. How can I
divide this to produce the 50% duty cycle 4Mhz signal?. Is it even
possible with logic alone?. I can see how to mix with either 6Mhz or
14Mhz, but this then detracts from the required accuracy.

Several approaches spring to mind. You stated "accurate" - they all provide
that, but jitter is introduced in all of them:

1. VCO at 4MHz, divide by 4 and lock to Fref = 1MHz from your 10 Meg source
divided by ten.

2. VCO at a multiple of 10M - say 40 MHz - locked to your 10M ref and
divided down (by in this case 10) to give 4 MHz output.

Both of the above may provide acceptable jitter.

3. a no-VCO approach - frequency double twice using XOR gates, then divide by
five and finally by two in say a 7490. Simple glue logic chips.

4. use a micro.

I would certainly expect both 3 & 4 to present more jitter than well-implemented
VCO solutions. If jitter is critical to the application, this needs to be
indicated.