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Old March 14th 04, 09:58 PM
Paul Burridge
 
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On Sun, 14 Mar 2004 15:55:04 -0500, Active8
wrote:

On Sun, 14 Mar 2004 13:14:40 +0000, Paul Burridge wrote:

On Sat, 13 Mar 2004 20:23:45 -0500, Active8
wrote:

Just a rough guess, since your calling on supreme beings...


The post is still vacant as yet...
:-)

That input cap... I take it the input source is a reasonable
estimate of your square wave... if the time constant of that input
RC net isn't right, it'll be a differentiator, and turn your square
wave into pulses coincident with the rising and falling edges. Your
scope trace suggested otherwise, but IIRC, at that tin=me you were
using the filter at the input to the mult., xo things have changed.


There's been no filtering (other than the selective properties of the
tank circuits) whatsoever employed thus far.

It doesn't look like you're biased in Class C. All the mults I've
seen are Class C biased with the tuned circuit on the collector. And
remember, when you're doing this later for some other purpose, in
Class C, the transistors Vceo - reverse breakdown - must be at least
twice the supply voltage.


Yup, perfectly correct. I must admit that going the class C route with
the tank tuned to the required harmonic was the way I was 'brought up'
as it were. Class C typically generates lots of harmonics as you
obviously know. This multiplier seems to be operating in class A,
which I admit is odd given its high linearity. But I didn't design the
multiplying stage you see here, but the guy who did is an RF expert so
I don't argue. :-)

But you've just given me an idea: maybe I should increase the value of
the 82 ohm base-ground resistor to increase drive signal level and tip
the stage into class C. Worth a try?


Nah. With a *sine* input, you'd bias it so it only conducts for less
than 180 degrees of the fundamental's cycle - keep the trans *out*
of conduction for the most part. Now that I think of it, yer using a
square wave and should have the stinkin' harmonic already, duh. What
was I thinkin'? I still wonder what that input cap is doing to the
edges. The trace you posted indicates it *might* be ok if nothing
changed.

Just for grins, get rid of that input cap and do whatever with the
bias to allow you to DC couple the multiplier. That's pretty class
C'ish assuming a 0 - 5V square wave. Don't fry your b-e junction.
Something's wiping out your 5th, so lets get that input RC outta
there.


Hi Mike,
I'm made your suggested changes and re-run the sim.
The new output result across the 1k resistor is now viewable on
abse....

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