On Thu, 18 Mar 2004 11:33:17 +1000, Tony wrote:

On Thu, 18 Mar 2004 10:42:22 +1000, Tony wrote:

Ignoring most of the previous posts in this thread (sorry - I deleted them) it
occurs to me that maybe the problem may be the relatively low impedance load on
the buffer, whose finite output impedance therefore causes some waveform
distortion and loss of 5th harmonic. So how about a hi-Z parallel tank coupling
circuit; for 17.2MHz (say 4p7 || 18uH) into a load of 100-500 ohms (say a 1k pot
+ 100n to Gnd, to see the effect of load variations), then into another 74AC
buffer?

Tony (remove the "_" to reply by email)

Actually the tank's output will be biased to half-rail, which won't necessarily
bias the CMOS output buffer properly. May need to cap-couple to the buffer, with
a feedback resistor so it will self-bias (another case of reading the post AFTER
hitting "send").

There's a lot of that goes on here. :-)
I'll look into the idea, thanks.
--

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