In article , Paul Burridge
writes:

On Sun, 21 Mar 2004 16:02:18 GMT, "W3JDR" wrote:

Airy,
What you said would be relevant only if you were trying to determine circuit
losses due to "unloaded" Q of the components. I believe Paul is trying to
determine the 'loaded" Q in order to obtain best selectivity (narrowest
bandwidth). Is this true Paul?

Some clarification is necessary!
The application is the tank in a frequency multiplier.
I am seeking to select for the 5th harmonic. Therefore, the tank needs
to have as little loss as possible given the fact that the 5th will be
way down dB-wise on the fundamental. I can't afford to attenuate it
too much as it's already weak to begin with. Ergo, I need the lowest
loss components and the best selectivity for the desired 5th harmonic.
Thanks,

Design of that is a two-step process. First, you need to establish
the impedance (or admittance) of both source and load. For a
parallel-resonant circuit selectivity device, they are both in parallel
with the unloaded Q of the resonant circuit. For a series-resonant
selectivity device, they are in series with it.

With vacuum tube and FET circuits, staying in the linear I/O bias
region, the first step is easy. Just parallel drain or plate resistance
and a gate or grid circuit resistance for a parallel-resonant circuit.
With bipolar transistors, the base resistance is quite low compared
to tube (valve) and gate inputs, must be impedance-magnitude
adjusted such as with tapping down on an inductor. There are
several other ways to do impedance-magnitude adjustment; that
coil tap is a very common one.

Once into a non-linear operation region the overall impedances
become dynamic rather than static and depend on drive level and
the amount of time an input spends in non-linear region versus the
linear region. Using digital logic devices means that the non-linear
regions are above saturation and below cutoff but the saturation
does not behave the same as with valve grid current run positive
on part of the cycle. That is NOT easy to calculate and quite
complex for those who take the time to do that.

For home workshop design efforts in getting to the task in the
most expeditious way, simply Cut And Try. Reg Edwards
pointed that out semi-directly. :-)

The second step is to select and inductor with, for your needs
in being selective to that elusive 5th harmonic, of the highest Q_u
(unloaded or "not in-circuit" quality factor) that will fit in the space
(physical space) you've alloted. That selection is a compromise
in size - cylindrical or "solenoid" cores mean (as Reg said) the
bigger the better. I'll also add "the bigger the wire diameter, the
higher the Q" for the same coil former size. For iron powder
toroid forms, the powder mix is important as well as the size as
well as the wire size.

Just from memory of a few years ago, a Micrometals T37-6 core
(the "37" meaning 0.37 or 3/8ths inch, powder mix 6) will yield a
Q_u of 80 minimum at 18 MHz using the largest wire that will fit
through the center hole. Q_u at 17 MHz will be very close to that.

Unloaded Q is a result of many factors and all of those can be
modified by things such as the dielectric material of a solenoidal
former and the presence of adjacent shielding and even dielectric
material. For the easiest application and less time worrying nit-
picky details, pick an iron powder core toroidal form...such can
be smaller than cylindrical formers allow and are much more
forgiving of adjacent/nearby objects. But only if space is at a
premium. Small toroidal forms can be difficult to wind for some
and multi-turn inductors need lots of wire which can build up in
the center hole, precluding use of larger magnet wire diameters.

Part of the second step is to combine what you know (or guess)
in the first step with a selection of inductance and capacitance
for resonance. As others have said, inductive Q_u is the
determining factor at HF and capacitive Q_u will be at least 10
times higher, probably in the neighborhood of 500 to 1000 for
ceramic or mica capacitors. Do a quick model of the resonant
circuit "resistance" (actually the magnitude of impedance) at
parallel resonance - parallel the (inductive Q_u times inductive
reactance) and the (capacitive Q_u times the same reactance
since capacitive reactance is equal to inductive reactance at
resonance). Parallel that with the source and load impedance
magnitude combined magnitude and you have the total magnitude
at resonance. This can be very quick to do with a scientific
pocket calculator.

To verify the selectivity, run the whole thing again at adjacent
harmonics to get the total magnitude of impedance there. Those
off-resonance L-C circuit magnitudes can use just the reactance
as an approximate step and be very close to those using the
unloaded L-C Qs. The ratio of magnitudes on-resonance versus
off-resonance will give you a picture of the selectivity possible.

If that "doesn't seem to be good," THEN pick a different L:C
ratio and do it again...but use what you know about the inductive
Q_u at that different inductance. Compare the new on-resonance
impedance magnitude to the adjacent off-resonance magnitudes.
Is that magnitude ratio worse than before? If so use an opposite
L:C ratio. If better, try the same-direction different L:C ratio and
compare that. If better, repeat. If worse, hold on the previous
L-C combination...you are zeroing-in on what is useful.

SELECTIVITY is the thing desired in your application and the
relatively-simple calculation of magnitudes and resulting ratios
will point in the right direction for something to try in hardware.
Selectivity is needed because the lower harmonics have more
energy than the 5th.

If stumped for a starting L and C value, try the literature on
previous multiplier designs as a starting point...then dance
through this two-step procedure.

In practical hardware, many others besides myself have been
led astray by simplistic "L:C ratio Q determination rules" that
can be just the reverse. Lots of those old maxims were
generated way back in time of large "coils and condensers"
one needed both hands to pick up...

Len Anderson
retired (from regular hours) electronic engineer person