RadioBanter - View Single Post

May 28th 04, 01:32 AM

In article ,
(Deepthi) writes:

Hi!
I need help understanding a conventional phase/frequency detector.I
consists of 6 two input NAND gates and 3 three input NAND gates.It
compares the phase and generates UP and DOWN signals.I was wondering
why the dead zone is high specially when there is a large reset delay
path.
Deepthi

The "conventional phase-frequency detector" I know is the basic
circuit of the Motorola MC4044 package. That one is explained in
detail - in the form of a timing chart of ALL gate states with little
arrows indicating which gate acts on other gates - in the
September, 1982, issue of HAM RADIO Magazine in the "Digital
Techniques" column titled "Inside A Phase-Frequency Detector
(MC4044)." The particular timing diagram is rather straightforward
waveform diagrams rather than the symbolic logic-state graphics
others have used. I am the author of that column.

The "dead zone" you mention is due to differential gate delays
and can be minimized with high-speed logic families. It has
several causes depending on whether the signal input is leading
or lagging the reference input. The waveform diagram lets you
select either one and, with a schematic, see the path that causes
the differential gate delay.

Len Anderson
retired (from regular hours) electronic engineer person