In article , "Steve Nosko"
writes:

"Avery Fineman" wrote in message
...
In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK"
writes:

There are various fixes for the dead zone problem.
In the mid-1970's, Fairchild (the original company)
sold an "11C44" phase detector that got rid of the
dead zone by injecting a narrow pulse so that the
phase detector pulses would never have to try to
go to zero width. Eric Breeze holds the patent
on this technique; if interested read his patent.
Analog Devices makes that AD9901 phase detector
which gets around the dead zone by first dividing
the frequency by 2. However, it is not suitable
for a frequency synthesizer because of the large
spurious sidebands resulting from this technique.
Motorola had some patents on the circuits in its
MC145159 that dealt with the dead zone and sampling
sidebands. It also used a divide by 2 technique, that
was not documented; (we figured it out by observing
the chip's output). That chip may have been inherited by
On Semiconductor. It was originally developed for
some division of GE.

The "dead zone problem" is less a problem and more a
state of mind. :-)

When implemented with a charge-pump circuit (voltage
& time converter to current) between the PFD and loop
filter, it rather disappears into the woodwork of the whole
PLL. The phase difference between signal and reference
is proportional to the control voltage of the VCO producing
the basic frequency. There is ALWAYS going to be a
signal versus reference phase offset when the entire loop is
in lock so this dreaded "dead zone problem" will only show
up in a very narrow range of controlled frequency.

General intuitive thought on any PLL or other synthesizer
closed loop is that the relative phase between signal and
reference is zero. It isn't. If it was, then the VCO could not
be controlled. As a very rough indicator of VCO frequency,
that signal v. reference offset phase exists for quick scope
checking...when the control voltage range of the VCO is
known. Good for a quick bench check.

In practical terms, that dreaded "dead zone" isn't visible in a
real-world example.

Case in point: 23+ years ago, Rocketdyne Division of
Rockwell International (now a Division of Boeing) was beginning
work on a Deformable Mirror for laser work (they had a sizeable
optics group) that used a 1 MHz signal out of optics to indicate
the light phase error of an optical interferometer. I rigged up a
74H family phase-frequency detector circuit as the heart of that,
an integrator out of that into an A-to-D converter to get a digital
version for computer data manipulation. By all the careful
measurement, the expected dead zone didn't show up on any
graphing and the standard lab time interval counters could
resolve, accurately, 2 nanoseconds using time averaging.
[translates to rather less than a degree of phase error] The
optical physicists had been hopping up and down about "dead
zone" in meetings but the actual circuit performance didn't show it.

One reason for the non-observation of any dead zone is that the
digital gates forming the PFD were so lightly loaded in other-gate
capacitance that their propagation delays all tended to be the
same. Datasheet values of propagation delay of gates are all given
as maximums, rather worst-case things with lots of pFds connected
to outputs, etc. Put on half a prototype board, loaded only by other
gates of the PFD and the resistor input of an op-amp integrator, the
capacitance loading was minimal. [project was successful, and
spawned more work on deformable mirrors]

It can be an interesting academic problem to achieve a zero dead-
dead zone effect in a PFD, but thats about it. When working at
the comparison frequency of less than a few MHz, the PFD dead
zone due to differential propagation delays of the gates disappears
into the woodwork when using 74LS or faster digital families.

There's plenty to be concerned about in any frequency synthesizer
subsystem, but a phase-frequency detector gate structure is a
very minor problem in my opinion.

DDS and fractional-N loops in synthesizers have their own problems
such as spurious output, but those problems can't really be traced
to any PFD dead-zone effect. A PFD is wonderful as a control loop
element in that it can control a VCO (of the loop) from way off the
frequency and bring it into a lock phase range...from either worst-
case start-up frequency. [way back in the beginning of radio time,
lock loops had to use sawtooth sweep circuits to cure that start-up
condition, and couldn't control beyond +/- 90 degrees of phase
shift...PFDs easily handle +/-180 degrees]

Len Anderson
retired (from regular hours) electronic engineer person

Len - Avery, whomever,
Our experiences differ. When designing PLL synths back then for two-war
radio, we always saw the dead zone.

"Two-war radio?" PRC-25? Term not understood. Experience has
hands-on with everything from a PRC-8 to a PRC-104, but little with
the PRC-25 or -77.

In a type 2 loop (hope I'm remembering
my control theory correctly) the extra integration allows the VCO to float
around within the dead zone, causing a low freq rumble at times. You could
watch the phase wandering around on a scope on the two PD inputs.

If the loop is set for something like a 10 to 50 mSec lock-in time,
one has to look quick to see the actual lock-in. If the loop is
designed properly (VCO control voltage gain, time relative to the
reference frequency), there should not be any "wander."

In order to see the settling time from a large step-function of
frequency change, you need to sync a scope from the step
source and watch the jump-and-settle of the control voltage like
a damped sinewave. That's a quick check of loop control
action. Storage scope (old way) or digital scope (muy better)
are the best way to view that.

We would
force some small leakage current just to hold it up against one side of the
dead zone. Perhaps the types of requirements causes the difference. We
were in the audio range with the PD reference freq and lock times in the
tens of ms. if I recall correctly.

Most of the older PLLs had reference frequencies of 1 to 5 KHz.
That's a period of 1.0 mS to 200 uS. Without about 5 to 10
cycles for settling-in (to near invisibility), that would be about
10 to 2 mS, rather quick.

If I recall, the Fairchild chip did a better job of matching the delays.
The small overlap causing a narrow pulse to occur seemed like a small
issue - not much energy at the ref freq for some applications. Our
synthesizers were of such requirements that there was a very tight balance
between lock time and spurious. The loop filtering took much care to get
the lock time and keep reference spurs down.

Regardless of the loop filter type, those are always fussy to avoid
pickup contamination of the VCO control line. But, knowing the
control voltage characteristics (delta-V v. frequency) over a range,
the design is strictly textbook formula stuff. It helps greatly if the
VCO control characteristics are linear versus frequency AND the
division ratio maximum to minimum number is as small as
possible.

I've seen a few applications where both the control voltage
characteristics were very non-linear AND the division ratio of the
PLL greater than 2:1 with the end result being an almost
impossible lock at the extreme ends of the tuning range. One
case was alleviated by extra circuitry from the division control to
generate a DC bias summed with the control voltage. Not too
swift since it took more parts, but better than failure.

In my own case, the filtering and shielding around the PFD to
VCO had to be rather severe in order to keep it stable (too
much high-energy circuitry rather nearby). Once that was
achieved, there was no wandering at a 1 KHz reference input
with proper values of known control voltage constants and
accurate calculation of loop filter values. It was "tight."

Len Anderson