In article bWTtc.11435$eY2.451@attbi_s02, "Rick Karlquist N6RK"
writes:

Let me try again to explain dead zone.

Many PLL's never experience the dead zone because the loop
filter is constructed using op amps with high (10 mV)
offset voltage specs. This offset forces the loop to
lock up outside the dead zone.

With any phase-frequency detector, the width of the output
rectangular wave (from the digital portion) is proportional
to the control voltage output. That width can be converted
to a DC control voltage by a charge pump (pins 4, 5, 10, 11
in either the MC4044 or 11C44 package) or done externally
in an integrator such as with an op-amp.

When locked, the signal and reference inputs of the PFD will
be in-phase but the relative phases are offset in time. It is
that offset which eventually produces the control voltage that
brings the VCO into the in-phase condition.

A "dead zone" does indeed exist in all such circuits but it
will take effect ONLY in the VCO frequency region where the
phases of signal and reference input are the same or very
nearly the same. At any other VCO frequency the "dead zone"
has no effect since the phase offsets of signal and reference
are away from that "dead zone." Note: The signal and reference
phases will be "in-phase" meaning that they are both on the
same frequency but the signal is offset in phase from the
reference.

The "offset" of any extra circuit elements to an op-amp used
in coupling the PFD to the VCO can be used as a stop-gap
cure for the "dead-zone" but that still is effective only in the
phase relationship of the signal v. reference inputs where they
are nearly the same phase.

If you use a low offset op amp,
and then put in an offset adjust pot to take out any
residual offset from the phase detector, you can observe
the spurious sidebands at the phase detection frequency
null out.

Observation shows the entirety of the loop action. It does
not pin down a cause of the spurious outputs. Those spurious
outputs can be caused by a number of different things.

However, you will then find that the loop bandwidth
has changed substantially, because you are in the dead zone
region. The VCO will get more phase noise because the
loop wanders around (like a bang-bang loop) in the dead
zone, and/or the change in loop bandwidth has de-optimized
the suppression of VCO noise by the PLL.

The VCO control voltage curve sets part of the loop filter's
frequency response and is called the "gain" of the loop
feedback. Bandwidth is dependent primarily by the
reference frequency plus the lock-in response time desired.
Too much "gain" and the whole loop goes into oscillation,
never settling down; too little and the loop takes a very long
time to lock in (and may never do so). Curvature of the slope
of the PFD output (converted from time to voltage) affects the
"gain" and thus the total closed-loop condition.

I have
personally observed this and other engineers I have
mentored have also observed it (after first arguing with
me that it wouldn't happen).

The "dead zone" does indeed exist but I'm simply saying that
(1). It isn't an ogre ready to strike fear in use; (2). It doesn't
effect a PLL lock over all VCO frequencies...just that narrow
range of VCO frequencies where the relative phase offsets of
the signal and reference inputs to the PFD are about the same.

The original question involved a six 2-input, two 3-input, and
(one 4-input) gate EQUIVALENT of the '44. That original '44
design is an elegant one, a sort of gigantic flip-flop on steroids
which will work over a +/-180 degree range. It is far superior to
the old types of phase detectors which had only a +/- 90 degree
operating range. The time characteristics (or phase relationship
of input rectangular signals) of such a circuit can be much
improved by using faster-responding digital logic families. By
using 74F or 74H or other very fast gates, the "dead zone" can
be made very small, enough to essentially forget about any such
effects on the overall PLL with a 10 KHz or lower reference
frequency.

If there is anxiety over the PFD operation, it can be examined
with a 'scope and a stable, delayed signal pulse synced from
the reference input. The '44 circuit type doesn't need square
waves but can operate solely on leading edges. With a time-
interval-averaging counter, the signal input phase can be set/
characterized very accurately as well as the output pulse width.
Lacking a time counter, a 'scope (hopefully with delayed time
base function) can be used for coarser measurement. The
'scope will display the "dead zone" condition.

To correct previous misinformation about the 11C44: the
gates are not better matched; rather there is an extra pulse
injection circuit as described in Eric Breeze's patent.

That's not included in the diagram shown on the 11C44 data
sheet website you referenced. That gate diagram and charge
pump and Darlington bipolar circuits are exactly as in the
original Motorola '44 data sheet. Either PFD gate arrangement
can be duplicated using "discrete" logic gates.

In my opinion there's an elegant simplicity of the '44 gate
arrangement which adequately fulfills its purpose of not only
operating over a +/- 180 degree input phase offset but also
staying on extremes of low or high frequency signal input
condition, ideal for PLL start-up. I'd like to know the original
circuit designer to send thanks for such elegance in circuitry.

Other manufacturers (such as RCA and Intersil) have duplicated
the '44 PFD gate arrangement with success. It can be copied
with ordinary logic gates without problem. If there is a region of
a PLL to concentrate on, I'd say it is in the pulse width to DC
control voltage following circuit and the loop filter (and its
shielding and isolation).

Len Anderson
retired (from regular hours) electronic engineer person