Steve,
Good job. I concur 100%.
I quickly gave up on arguing this as it became clear to me that the number
of words expended was increasing exponentially with the length of the
thread. Arguing with some people is like surfing the web...you send a few
bytes up and megabytes come back at you. I don't have the time or energy to
play that game.
Right is right, and wrong is often long-winded.
Thanks for the support.
Joe
W3JDR
"Steve Nosko" wrote in message
...
"Avery Fineman" wrote in message
...
In article , "W3JDR"
writes:
To Len:
Not quite it. In order to derive a control voltage for the
controlled
oscillator, the PFD output MUST BE A FINITE WIDTH....
...BUT THERE IS ALWAYS A PHASE OFFSET.
Len,
This is actually _not_ the case as Joe (W3JDR), says.
Summary: The charge pump drives CURRENT into the main loop filter
capacitor forming another pole (at the origin, if I recall my control
theory
correctly) or _integrator_.
Detail = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
=
= = = = =
The charge pump is set up as follows. The PFD has two outputs, an UP
and DOWN. The UP output produces an output which is "active" or high
(lets
make everything positive-true logic for this discussion) for a time period
which is the time from the edge of the reference to the edge of the VCO.
So
that when the VCO drifts down, its edge is later and we get pulses. In
other words, we get pulses out equal to the time difference of the edges.
The DOWN is the converse.
Each output drives one half of the charge pump and as long as that
output is in its "active" state, the charge pump is providing _current_
into
the main loop filter capacitor. (lets assume that UP "pulses" means the
VCO
it too low and VCO freq is proportinal to control voltage) When you get
off
freq. the respective PFD output hits the rail and is in a _constant_ UP
state. Therefore, that half of the charge pump drives current into the
capacitor causing it to charge up at a rate equal to I/C. This is a
simple
re-write of the capacitor formula I = C * dv/dt. This effect is another
integrator in the loop which gets you to zero phase error. As long as
there
is a phase error, there will be a _CHANGE_ in control (or steering) line
voltage until you get to zero phase error and a stable control line.
If I again recall my control theory, this makes it a type 2 loop.
This does TWO things.
1) It drives the PFD pulses to zero making them as small as the logic
will allow thus
leaving the least amount of reference frequency energy to be
removed
and
2) The integrator attenuates the higher freq harmonics of the
reference
pulses that remain.
To be honest at this point, the loop filter will be a lag filter
which has
a finite high freq atten, but some loss none the less. Other
filtering is usually
required to further reduce the reference spurs. In communications
PLLs the fight
is between the filtering required to get the reference spurs down
to
the desired
level and the classical lock time determining "loop filter". This
is because the phase of the reference spur
low pass filter starts to eat into the loop's phase margin and
cause
more
ringing (poorer damping factor) as you require more reference
attenuation.
= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
=
= =
......
OK, so where is the VCO control voltage coming from and how does
it "know" how to reach the right voltage for the right frequency?
From the loop filter capacitor which stays charged when the PFD shuts
up
at zero phase error.
...
...There will ALWAYS be a small error in any control loop...
otherwise a control loop couldn't function to do controlling (basic
control loop theory which so many seem to forget).
You are thinking of a type one loop and that's ok... Add the
integrator
and (by theory & practice) you get zero phase error. I majored in control
theory & designed 2-way mobile PLL synthesizers. I also believe I
designed
and built the first amateur, PLL synthesized 2M handheld (Motorola HT220)
in
1973.
A "charge pump" is basically a voltage-to-current converter to...
Actually, Len, the charge pumps I designed were a
phase-to-*current*
converter. (Actually an edge-time-difference - to - current converter.
That is, when combined with the PFD. By itself, it was a pulse to current
pulse converter. It was a current source which was turned on during the
pulse. (two--one for UP & one for DOWN). Perhaps it should be called a
"gated current source". During the UP or DOWN pulse, the respective
current
source is turned on at its full current.
... zero propagation delay to make such a...
If I recall the Fairchild improved 4044 used MATCHED delays in the two
paths to minimize the dead zone as well as the opposite effect, overlap.
...The '44 is more complex...
If there are more than two signal edges for every reference edge,
the outputs hold at one state indicating a "way-off" ...
Yea, off frequency. So you DO know how it works by this statement.
The
phrase "hold at one state" _IS_ the key here in the charge-pump circuit.
It
will "hold the charge pump transistor on", continue to supply current
(charge at a constant rate) to the cap causing the voltage to keep rising
and the frequency to keep changing. When the phase error is zero, then
the
control line stops changing and the VCO is on freq.
An op-amp integrator circuit functions as a sort of time-to-current-
to-output-voltage converter ...
Ahhh! The "charge pump" does the same thing as a regular
integrator.increasing the loop type.
Based on hands-on observation . the PFD outputs
ARE pulses at the reference frequency. Their width
is proportional to the integrated-averaged DC control voltage of the
VCO when in lock.
You may have lost me here, Len. I think, in the type 1 loop
you
describe, the control voltage is the average-of-the-pulses (the phase
error). I think you mean the "average of", not "integrated average of".
With the type 1 loop the VCO control line voltage would be the average
of
the phase error. So you would indeed require an error, but that's why we
add the integration function in some loops.
Please note that by virtue of the VCO (having a voltage-to-frequency
transfer characteristic) and the Phase detector (having a phase to voltage
characteristic), there is already one built-in integration in the loop.
This is because phase is the integral of frequency...or is it the other
way
'round. (i always have to stop and draw a figure to state this freq/phase
integral relationship...les-see...- a step freq change integrates to a
ramp--phase is the integral of freq, yea, that's it )
As I said earlier, I have watched the loop bounce around the dead
zone -
bumping up against the ends of the (zero phase) dead zone and producing
mini
correction charges to correct the frequency. I would often force some
small
current (sometimes with a reverse biased germanium diode) to stop the
rumble
by forcing a small phase error.
Each integration in the loop gets you another level of "in lock"
accuracy. (i forget the official term), but.
First is a frequency locked loop where, as you say here, there must be a
small Frequency error to obtain the VCO voltage. Such as using a VCO with
a
discriminator instead of a PD. (frequency type 0)
Second is frequency lock loop with fixed phase error. (frequency type 1 -
phase type 0)
Third is the one with zero phase error. (frequency type 2)...etc
Each increase in type (or addition of a loop integrator) gets to a true
_zero error_ for a higher order of input change. Starting with (although
trivial a frequency locked loop with finite frequency error), freq, then
phase, then ramping phase, then second order phase change (squared) ...but
i
digress...
...the "way-off" (phase errors larger than 180 degrees) conditions of
the PFD outputs REMAIN in their fully-on ...
This is what Len meant, I believe, by "constant pumping". Not your
usual, water-well pump metaphor, Len.
You get near the subject of "Capture Range" and "Lock Range" next.
The
XOR type PD has a lock range , or "pull-in Range" determined, in part, by
the loop filter. More correctly by the loop bandwidth. If some of the
XOR
output square wave can't get through the loop filter (by being a low
enough
frequency) and drive the VCO toward the desired frequency, then it can't
lock from far off freq. So it has a finite capture or pull-in frequency
range. The PFD has an infinite pull-in (within the rails) per the above
operation.
...However, integrated-averaged to DC, the outputs of the PFD make
an excellent phase meter .
(again I dislike the term "integrated average" here, but think
"average"
is what is intended) Very true (Without the charge pump). Just averaging
the pulse width (phase difference). It is a phase-to-voltage converter.
Then voltage makes the VCO get to freq.
...Ain't no "pump" pulses whatsoever at those "way-off" conditions.
Very true if you mean "pulses" with an off-time in between. Just a
steady always on "pump" current at full current. This translates to
"maximum ramp speed" of the VCO control line.
Joe
The XOR's big advantage is that it is simple, and there is no
discontinuity
around the phase lock point (as there is in the PFD), but it does not
lock
up readily in the face of frequency errors.
You should say; "in the face of _large_ frequency errors".... the
"Capture Range" problem I mentioned above.
Joe:
The PFD's advantage is that it
readily locks up, even in the face of large frequency errors and it
also
produces an easily filtered output.
Yep. Sorta' the ideal. Almost zero reference pulse energy and pull-in
range limited by the PFD rails and VCO range only.
When you get the chance, grab a 'scope and look into the
waveforms of a PFD as well as the control voltage. You will
find out I'm right. No "theory" on that, just working PLL
hardware.
As long as you have no charge pump or integrator, you are 100%
correct.
Len. All the Motorola Pulsar car phones used the same charge pump for 0
phase error. This is still used now, but fractional N methods allow small
steps in freq (~5 kc) with high reference frequencies (~2 Mc) at the
expense
of more logic.
If I confused who said what, I apologize.
--
Steve N, K,9;d, c. i My email has no u's.
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