all of them will work at a
better buffer between the vco and the following PLL. the simplest
solution is use a grounded gate FET amplifier between the PLL input
and the VCO output. be careful though, such a configuration is almost
gaurenteed to self oscillate. but that is easily taken care of. what
you do is this .. solder the FET upside down with its legs sticking
up. solder the gate to the ground with as small a lead as you can.
then, using a thin copper sheet or an unetched pcb, make a sheild that
is soldered vertically over the FET (with a cutaway to allow the FET
body). keep the source and drain leads on opposite sides of the
sheild. bias the FET for nominal current at about half the Idss.

Yes, that also sounds for me the best thing to do (improving buffer
between VCO and PLL). Well, I'm not experienced with such circuits, so
could you just explain how to bias the FET.


VCO o-||-- S-D --||--o OUT TO PLL
^ FET=MPF102 or stg like that
G
|
o----------------o GND


And one last thing, could you re-explain how you advise to shield the
FET ? I don't see what you mean :-(

Thanks for your answer ;-)