"Paul Burridge" wrote in message
...
Hi all,

In his very skimpy explanation on basic DC biasing for FETs, Chris
Bowick (in RF Circuit Design) gives the suggested bias network that
I've posted to a.b.s.e under the same subject title as this message.
I don't see how this arrangement can possibly work for any N-Jfet
since for one thing at least, the gate is positive with respect to the
source. I've tried to scan the page in and post that, but the
scanner's messing about, so I've redrawn it as a spice schematic and
posted that instead. If it turns out the arrangement is incorrect, as
I suspect, I will endeavor to post his explanation for how he arrived
at these resistor values.
So: is he wrong or am I nuts?

Have a look on the inside flap to see if he's a reader in engineering at
some University. If so, then they probably are errors.



p.

Note: for anyone using LTspice, the fet shown is not a working model;
I'm simply posting this as a diagram for illustration.
--

"What is now proved was once only imagin'd." - William Blake, 1793.