On Thu, 12 Aug 2004 18:54:55 -0400, Active8 wrote:

On Wed, 11 Aug 2004 12:59:22 -0700, John Larkin wrote:

On Wed, 11 Aug 2004 20:46:24 +0100, Paul Burridge
wrote:

Hi all,

In his very skimpy explanation on basic DC biasing for FETs, Chris
Bowick (in RF Circuit Design) gives the suggested bias network that
I've posted to a.b.s.e under the same subject title as this message.
I don't see how this arrangement can possibly work for any N-Jfet
since for one thing at least, the gate is positive with respect to the
source. I've tried to scan the page in and post that, but the
scanner's messing about, so I've redrawn it as a spice schematic and
posted that instead. If it turns out the arrangement is incorrect, as
I suspect, I will endeavor to post his explanation for how he arrived
at these resistor values.
So: is he wrong or am I nuts?

p.

Note: for anyone using LTspice, the fet shown is not a working model;
I'm simply posting this as a diagram for illustration.

Looks like the jfet will be saturated with the values shown, not good
for RF work. Looks like he got the sign of Vgs backwards.

Well, when you rearrange the Id eq to get Vgs, you get

[ ]
| |
| ( ) |
| | I | |
| | D | |
V = -Vp| sqrt| ------- | - 1 |
GS | | I | |
| | DSS | |
| ( ) |
| |
[ ]

You can swap the terms inside the brackets by moving the negative
sign of Vp inside, which gives you Bowick's version. Either way, you
get the wrong answer unless you recall that

sqrt(4) = +/- 2

So you have to apply some reasoning.

Strike that. I'd didn't work. Gots me wondering WTF now.