On 11/22/2012 1:07 PM, Rob wrote:
I have been able to write some DSP code that way, even on a dedicated
DSP in asm (which has the extra complication that you need to learn the
instruction set, that looks quite different from a normal CPU), and
it was fun.

DSP doesn't have to be code. In this case it will be hardware in an
FPGA. So the calculations will all be done in dedicated hardware. I
don't plan on doing multiplies, but that might happen. These chips
don't have dedicated multiplier. I've done multiplier designs with the
shift and add algorithm, not so hard.


However, before that DSP experiment I sometimes wrote code that looked
for zerocrossings and timed the duration between them, and tries to
decode data from that, and that is the wrong approach when you want
good performance.

Actually I did a commercial design that way for demodulating a time code
signal. It only needed to measure amplitude to get the data, but had to
sync to the carrier for "precise" timing. Looking for the zero
crossings was a very effective method with an 8 kHz sample rate on a 1
kHz carrier that had a very high SNR.

Rick