On 3/7/2013 2:39 PM, Jeff Liebermann wrote:
On Thu, 07 Mar 2013 13:11:03 -0500, wrote:
I understand. But this is intended to be *very* low power and I haven't
found an amp I can use that is in the low double digits uW power
consumption range. I plan to use no amp and go straight to digital.
I don't think that's possible. Unless your input A/D converter can
operate in the microvolt region, it's going to have a difficult time
dealing with the low signal levels. Fortunately, WWVB is on-off
keying with no amplitude component, so there's no incentive to add an
AGC controlled input amplifier in order to maximize the A/D converters
dynamic range. Still, you need to work with something more than a few
bits above the noise level. Incidentally, after midnight, you WWVB
delivers about 100 uV/meter or more to continental US.
http://tf.nist.gov/tf-cgi/wwvbmonitor_e.cgi (Java required)
I've seen it strong enough that I can see the waveform on an
oscilloscope after a 60Khz passive filter.
Yes, I have done my homework on the WWVB signal. I am at the fringe of
the 100 uV/m contour. I would very much like to see the signal on an
oscilloscope when I test this. They have a receiver not far from here
in Gaithersburg, MD and the signal is often strong during the day. So
much so that I don't follow why they say there is this day/night signal
strength fluctuation. It looks much more random to me.
The WWVB signal is not truly on-off keying. I believe they use a 10 dB
modulation factor for the AM signal. This is close to on-off I agree.
But they also phase modulate the signal and I will be demodulating both
to see which one works best in my design.
The ADC in my design is truly one bit. It is an LVDS input on an FPGA.
I looked at delta-sigma (or is it sigma-delta?
conversion and got
code from the chip vendor for a simplistic implementation. I don't
think I have the power budget for that and am using a much simpler 1 bit
ADC at 4x the carrier rate. The bit stream is multiplied by quadrature
carriers at 60 kHz and each stream summed for 1/30 of a second to
implement what can be considered a DFT bin, a decimated FIR filter or a
decimated down conversion; take your pick, they are all mathematically
the same in this case because the sampling is synchronous to the carrier
(or very close to synchronous).
What comes out the other end of this processing gains nearly 40 dB in
SNR. My simulations show a recoverable signal when it is more than 20
dB below the noise.
Of course, I have not tested this yet on a real signal. I want to run
some tests on the antenna and coupling transformer to verify the
simulation. Then I will start working with the FPGA to see if I can
make the LVDS input do what I want. I have ideas on how to bend digital
circuits to do my bidding. This LVDS input is why I want as large a
signal as possible from the antenna. With the high impedance input on
the chip I should be able to boost the signal pretty well with just
passive devices and signal processing.
The loop antenna is rather large. I would like to end up with something
smaller. Once I get this working with a shielded loop antenna I will
check out the ferrite core antennas. My understanding is that they
don't produce as much signal.
As for bandwidth, the code is sent at 1 baud (1 bit/sec) which
produces about a 2Hz occupied bandwidth. Therefore, the maximum Q of
the antenna would need to be:
60Khz/ 2Hz = 30,000
before the antenna bandwidth becomes a problem.
I'm not sure how you came up with 2 Hz for the bandwidth. In this case
the bandwidth is not just twice the bit rate. I believe the stated
"system" bandwidth is around 5 Hz (from a 1995 paper prior to addition
of the phase modulation). Regardless, I am sampling at 30 Hz and if I
expect to see significant changes in phase or amplitude within one
sample time, I need an appropriate bandwidth.
Even so, that is not the limiting factor. The limiting factor is the
difficulty in holding tune with drift in passive component values. The
Q can be raised by increasing the turns ratio on the transformer, but it
becomes so sensitive to the parasitic capacitance that the sensitivity
drops 10 dB with a 1 pF change.
Incidentally, while Googling away merrily, I found this on SPICE
models for a loop antenna. It's not quite in your xformer format, but
it might be useful:
http://sidstation.loudet.org/antenna-theory-en.xhtml
I won't pretend to understand what the author is doing until I read it
more carefully.
Thanks. I will take a look at that.
Incidentally, I used a WWVB code simulator driving a signal generator
to test my receiver:
http://www.leapsecond.com/notes/wwvb2.htm
I will be needing a time code simulator. I designed a commercial
product that works with the IRIG-B time code which is similar. The
functionality is not hard, it is just a matter of generating the data,
encoding it into the modulation pattern, then impressing the carrier
with the modulation. Working in an FPGA this sort of stuff is easy.
The trouble is if you make the same mistake in both the generator and
receiver they work just fine in simulation, but not with other
equipment. lol
I'll take a look at this link.
If you're seriously into this, I suggest asking questions on the
time-nuts mailing list:
https://www.febo.com/mailman/listinfo/time-nuts
I might look into that. Certainly it can't hurt to get more input.
--
Rick