rickman wrote:
On 11/16/2014 11:14 AM, Joerg wrote:
rickman wrote:
On 11/4/2014 6:29 PM, rickman wrote:
I am working on a project for receiving a very narrow bandwidth signal
at 60 kHz. One of the design goals is to keep the power consumption to
an absolute minimum. I'm trying to figure out how to run a
pre-amplifier on less than 100 uW. So far I have found nothing. Any
suggestions?
I had found one op amp that might get me in the ballpark of power
consumption and I did some spice simulation on it. The current ends up
being in the 50 uA range which is more than I would like and the gain is
only around 100 before the bandwidth limits are felt which is less than
I would like. At 50 uA there is not the power to add a second stage.
Instead I was looking at some JFETs and found one I like, BF862 made by
NXP. I can construct a stage that gives a gain of 40 dB at only a
handful of uA. But when I try to cascade a second stage I have trouble.
The input capacitance is stated in the data sheet to be in the range of
10 pF. If I add a 10 pF cap to the output of the first stage I get
close to 40 dB of gain at the frequency of interest, 60 kHz. But when a
second stage is added with capacitive coupling the gain of the first
stage drops to 19 dB at 60 kHz while maintaining 40 dB at 1 kHz.
You need a FET with an input capacitance an order of magnitude lower.
Can you explain this? The info I have on the BF862 shows 10 pF range
gate to source. If I replace the FET gate with a 10 pF load on the
first stage the output looks normal. With the FET in place the
frequency response of the first stage output looks very bad with a
complex curve rather than just a simple capacitor loading.
Afraid I don't quite understand. If you mean replacing the 2nd FET with
10pF one possible explantion is if the whole thing was on the verge of
oscillating. If the 2nd stage is also 40dB that would be 80dB total, no
small feat. To reduce the chance of oscillations slip ferrite beads into
or onto each gate connection.
Miller will also have an effect which is why I suggested Cascode . A
dual-gate is a glorified cascode amplifier. A cascode avoids the miller
problem for the 1st stage almost completely because it keeps the drain
of the lower FET constant. In a dual-gate it's a "virtual drain" because
both FETs are inside one channel.
Got to run now and can't find it so quickly but ask John Larkin. He
suggested a FET a while ago that is IIRC under 1pF.
Dual gate FETs are another option. An example, although this one still
has 2pF at gate 1:
http://www.nxp.com/documents/data_sheet/BF998.pdf
Have you tried BJTs? Only sad thing is, many of the very low power
Japanese ones have been discontinued.
I know nothing about dual gate FETs. The BJTs I have looked at won't
get the high input impedance or the low biasing currents I want. The
JFET is operating with about 5 uA of drain current.
That's tough. Most JFETs are too big for that but it can be done.
Japanese companies used to offer smaller ones but no more.
As John said, if you can tolerate narrowband operation just around 60kHz
consider a resonant structure. Then the capacitances no longer matter.
--
Regards, Joerg
http://www.analogconsultants.com/