On 11/5/2015 8:27 PM, Jeff Liebermann wrote:
On Thu, 5 Nov 2015 02:44:24 -0500, rickman wrote:

How do you control the coupling in the real circuit? I was planning to
use a current transformer which I assume would be strongly coupled. Of
course, I was minimizing C2 which resulted in a high frequency second
peak far above the 60 kHz peak. I don't recall seeing a poor Q in the
circuit. Q is useful to minimize any nearby interference, but otherwise
my concern is max signal strength to get enough signal to be detected by
the crude FPGA comparator input.

The Q is approximately set by the ratio of:
tuning_capacitor / coupling_capacitor

Not sure where you get this. Q is a measure of the energy stored
compared to the energy lost. If the coupling capacitor were the only
path of lost energy that might work, but I've yet seen a situation where
that is the case.


However, that doesn't work with inductive coupling where the Q is
controlled by the inductors individual Q. I guess Q is the wrong
term. When you critically couple a collection of LC circuits, as in a
multi-section bandpass filter, the curve goes directly through the 3dB
bandwidth points, no matter how many stages are coupled. In other
words, the Q is set by the Q of one section.
What does change is the filter shape factor, which is the ratio of:
30_dB_bandwidth / 3_dB_bandwidth
or ocassionally:
6_dB_bandwidth / 6_db_bandwidth
????
depending on which reference book you're following. The first is more
common. Adding additional criticially coupled filter stages doesn't
change the Q, but really changes the shape factor. I can fire up a
filter design program to illustrate how it works, but not now.

You are assuming the two filters are coupled in a useful way. If the
frequency of the parasitic filter is far above 60 kHz it can be ignored
other than the possibility that it picks up a radio station which
clobbers the WWVB signal.


I'm also a bit worried about the way you're feeding your FPGA directly
from mag loop. The problem is that WWVB uses both an amplitude
modulated time code, as well as the new phase modulated time code.
Decoding the former is going to require some AGC (automatic gain
control) to insure that the FPGA A/D converter is not going to get
clipped, go non-linear, or offer too low a signal level to get a
decent SNR. The phase modulated signal doesn't have this problem, but
has patent issues if you're going to try an sell chips or devices.
https://en.wikipedia.org/wiki/WWVB#Phase_modulation

I didn't see anything about patents.

You worry far too much about "overloading" the FPGA input (single
comparator). My concern is being able to detect a signal at all.


Gone for a hot chocolate break...



--

Rick