"Brian Morrison" wrote in message
...
On Sat, 6 Feb 2016 14:10:10 -0000
"gareth" wrote:
Presumably those SDR rigs which do not work on the IF but
directly from antennae must have, separately from the DSP processor,
some semblance of a DDS generator (but without the final DAC) to
act as the equivalent of the VFO, for I cannot perceive that a
fractional-Hz tuning rate could be achieved with machine code running
in the DSP processor?
If you have a look here http://sdrplay.com/windows.html Gareth you will
find some links to 4 or 5 pdf documents covering various aspects of the
SDRplay RSP which is based on the Mirics MSI3101 chipset (comprising the
MSI001 and MSI2500 chips). It provides a maximum down-conversion
bandwidth of 8MHz at RF frequencies of up to 2GHz and can interface
with various DSP demodulator back ends such as HDSDR or SDR-Console
together with the necesssary device drivers to configure the chips and
set up the data paths.
That ought to help you see the topology of the receiver and you can
work out some of the various clock and VCO frequencies used for the
different RF bands covered by the switched front-end RF filters.

OK, by following onto ... http://www.mirics.com/Mirics_MSi001_002.pdf
I see fractional divide-by-N and a PLL combination integrated onto the chip,
which is along the
lines that I suspected, ie, a somewhat conventional approach outside of the
DSP.