CAN YOU GIVE ME COMMON PITFALLS MADE BY ENGINEERS IN PCB LAYOUT DESIGN
ON MY APPLICATION IN TERMS OF:
1.GROUND AND POWER PLANES
2.SHARED/NETWORK IMPEDANCE
3.STAR GROUNDS/ISLANDS
4.PARASITICS
5.PROXIMITY OF MY CHIP ANTENNA/SWITCH/AMPLIFIER

THANK YO SO MUCH!

mazerom wrote:

CAN YOU GIVE ME COMMON PITFALLS MADE BY ENGINEERS IN PCB LAYOUT DESIGN
ON MY APPLICATION IN TERMS OF:
1.GROUND AND POWER PLANES
2.SHARED/NETWORK IMPEDANCE
3.STAR GROUNDS/ISLANDS
4.PARASITICS
5.PROXIMITY OF MY CHIP ANTENNA/SWITCH/AMPLIFIER

THANK YO SO MUCH!


First, stop using capslock! We all hate people shouting!

2.4GHz?

If in doubt, add an extra PCB layer but be aware of the increased
capacitance. 4 layers? 6 layers costs almost the same price and makes it
easier to route for RF.

The Impedance seen into Power Deliver System at the device should keep low
from DC to several harmonics of clock frequencies on your PCB!

Use different layers for the 1.8V and the 3.3V and try to keep the impedance
well below 100milli Ohms.

Use NPO capacitors and if out of range, resort to X7R capacitors. This is
not a PCB problem, more a general remark.

Reduce parasitic inductance by:

Reduce the length of via for decoupling capacitors
(i.e.reduce the loop inductance)
Change the layout of decoupling capacitors
The thickness of high frequency capacitors
Parallel the decoupling capacitors with same value
or multiple skew values

Try to get your hands on any of the nifty simulation tools from Ansoft or
similar companies. Many of them have "student versions" of their packages.


Cheers




Have fun...


Cheers