On 3/8/2015 3:31 PM, Brian Reay wrote:
On 08/03/15 18:46, rickman wrote:
On 3/8/2015 9:53 AM, Brian Reay wrote:
Jerry Stuckle wrote:
On 3/8/2015 7:35 AM, Brian Reay wrote:
Jeff wrote:

I will finally point out that your use of the term "slope
detecting ADC"
is invalid. Google returns exactly 4 hits when this term is entered
with quotes. The name of this converter may have slope in it, but
that
is because the circuit generates a slope, not because it is
detecting a
slope. Please look up the circuit and use a proper name for it
such as
integrating ADC or dual slope ADC. The integrating converter is
not at
all sensitive to the slope of the input signal, otherwise it would
not
be able to measure a DC signal which has a slope of zero.

I'm only replying so that others are not confused by your
misstatements.



He is probably referring to a CVSD, otherwise known as a Delta
Modulator.

Jeff

I don't think so. In fact, I have to say Jerry seems a bit confused
in this
particular area, perhaps I have missed something.

ADC tend to have a sample and hold prior to the actual ADC
convertor, thus
the value converted is that at the beginning of the sample period
OR if
another approach to conversion is used, you get some kind of average
over
the conversion period. (There are other techniques but those are the
main
ones.)

If you think about, a S/H is required if the rate of change of the
input
signal means it can change by 1/2 lsb during the conversion time for
a SAR
ADC. This limits the overall BW of the ADC process. (I recall
spending
some time convincing a 'seat of the pants engineer' of this when his
design
wouldn't work. Even when he adopted the suggested changes he
insisted his
design would have worked if the ADC was more accurate. In fact, it
would
have made it worse.)


No, Brian, I am not confused. It is a form of delta modulation, but is
used in an ADC. Two samples are taken, 2 or more times the sample rate
(i.e. if the sample rate were 20us, the first sample would be taken
every 20us, with the second sample following by 10us or less). The
difference is converted to a digital value for transmission. On the
other end, the reverse happens.

Yes, the signal can change by 1/2 lsb - but that's true of any ADC.

For any sufficiently high sample rate (i.e. 3x input signal or more),
this method is never less accurate than a simple voltage detecting ADC,
and in almost every case is more accurate. However, it is a more
complex circuit (on both ends), samples a much smaller analog value and
requires more exacting components and a higher cost (which is typically
the case for any circuit improvements).

As I said - we studied them in one of my EE coursed back in the
70's. I
played with them for a while back then, but at the time the ICs were
pretty expensive for a college student.


Ok Jerry. You can, of course, find the rate of change (slope) by that
method if you know ( or assume) the signal is either only increasing or
decreasing between the samples. (A Nyquist matter).

However, the 1/2 lsb matter I mentioned is more for during the
conversion,
rather that for different samples. It is particularly important for
slower
ADC types, such as SAR implementations.

Can you explain your 1/2 lsb effect? What type of ADC are you referring
to? Different ADC types do require a S/H on the input for signals that
are not *highly* oversampled. For example a flash converter can mess up
and be quite a bit off if the signal is slewing during conversion. Same
with SAR converters. But I don't know of any effect where 1/2 lsb is a
threshold.

What threshold would you expect? As I recall, 1/2 lsb is the limit to
ensure that the conversion would be the 'same' over the conversion time.

I'm not sure what you mean by "the conversion would be the 'same' over
the conversion time", but I don't see how 1/2 lsb is any magic threshold.

If you are working with a flash converter, there are a number of
comparators each with a different threshold. The input signal could be
right at the edge of one of these thresholds so that a very tiny change
in the input signal will cause that threshold to be crossed during the
conversion.

Maybe I'm not understanding your point.

--

Rick

On 3/8/2015 9:53 AM, Brian Reay wrote:
Jerry Stuckle wrote:
On 3/8/2015 7:35 AM, Brian Reay wrote:
Jeff wrote:

I will finally point out that your use of the term "slope detecting ADC"
is invalid. Google returns exactly 4 hits when this term is entered
with quotes. The name of this converter may have slope in it, but that
is because the circuit generates a slope, not because it is detecting a
slope. Please look up the circuit and use a proper name for it such as
integrating ADC or dual slope ADC. The integrating converter is not at
all sensitive to the slope of the input signal, otherwise it would not
be able to measure a DC signal which has a slope of zero.

I'm only replying so that others are not confused by your misstatements.



He is probably referring to a CVSD, otherwise known as a Delta Modulator.

Jeff

I don't think so. In fact, I have to say Jerry seems a bit confused in this
particular area, perhaps I have missed something.

ADC tend to have a sample and hold prior to the actual ADC convertor, thus
the value converted is that at the beginning of the sample period OR if
another approach to conversion is used, you get some kind of average over
the conversion period. (There are other techniques but those are the main
ones.)

If you think about, a S/H is required if the rate of change of the input
signal means it can change by 1/2 lsb during the conversion time for a SAR
ADC. This limits the overall BW of the ADC process. (I recall spending
some time convincing a 'seat of the pants engineer' of this when his design
wouldn't work. Even when he adopted the suggested changes he insisted his
design would have worked if the ADC was more accurate. In fact, it would
have made it worse.)


No, Brian, I am not confused. It is a form of delta modulation, but is
used in an ADC. Two samples are taken, 2 or more times the sample rate
(i.e. if the sample rate were 20us, the first sample would be taken
every 20us, with the second sample following by 10us or less). The
difference is converted to a digital value for transmission. On the
other end, the reverse happens.

Yes, the signal can change by 1/2 lsb - but that's true of any ADC.

For any sufficiently high sample rate (i.e. 3x input signal or more),
this method is never less accurate than a simple voltage detecting ADC,
and in almost every case is more accurate. However, it is a more
complex circuit (on both ends), samples a much smaller analog value and
requires more exacting components and a higher cost (which is typically
the case for any circuit improvements).

As I said - we studied them in one of my EE coursed back in the 70's. I
played with them for a while back then, but at the time the ICs were
pretty expensive for a college student.


Ok Jerry. You can, of course, find the rate of change (slope) by that
method if you know ( or assume) the signal is either only increasing or
decreasing between the samples. (A Nyquist matter).


Even if the slope is neither increasing nor decreasing, it still has a
slope. That slope happens to be zero.

And with a sufficiently small time between samples, you will be very
close, even if the amplitude is not just increasing or decreasing. But
then sampling just the voltage assumes the voltage increases or
decreases linearly between samples. Again, the shorter the time between
samples (successive samples in this case), the closer that will be to
the actual signal.

However, the 1/2 lsb matter I mentioned is more for during the conversion,
rather that for different samples. It is particularly important for slower
ADC types, such as SAR implementations.


It's a problem with any ADC converter, and one to which there is no
answer. To perfectly recreate an analog signal you would have to have
an infinite number of bits (actually, some current physics theories
suggest everything can be broken into discreet pieces - even time, but
that's beyond this discussion). Anything short of an infinite number of
bits would always suffer from 1/2 lsb error.

It may well be that we are talking at crossed purposes. I'm not making an
issue of it.


Not really; you are correct with the 1/2 lsb, as I indicated.

--
==================
Remove the "x" from my email address
Jerry, AI0K

==================

On 3/8/2015 2:39 PM, rickman wrote:
On 3/8/2015 9:03 AM, Jerry Stuckle wrote:
On 3/8/2015 7:35 AM, Brian Reay wrote:
Jeff wrote:

I will finally point out that your use of the term "slope detecting
ADC"
is invalid. Google returns exactly 4 hits when this term is entered
with quotes. The name of this converter may have slope in it, but
that
is because the circuit generates a slope, not because it is
detecting a
slope. Please look up the circuit and use a proper name for it
such as
integrating ADC or dual slope ADC. The integrating converter is
not at
all sensitive to the slope of the input signal, otherwise it would not
be able to measure a DC signal which has a slope of zero.

I'm only replying so that others are not confused by your
misstatements.



He is probably referring to a CVSD, otherwise known as a Delta
Modulator.

Jeff

I don't think so. In fact, I have to say Jerry seems a bit confused
in this
particular area, perhaps I have missed something.

ADC tend to have a sample and hold prior to the actual ADC convertor,
thus
the value converted is that at the beginning of the sample period OR if
another approach to conversion is used, you get some kind of average
over
the conversion period. (There are other techniques but those are the
main
ones.)

If you think about, a S/H is required if the rate of change of the input
signal means it can change by 1/2 lsb during the conversion time for
a SAR
ADC. This limits the overall BW of the ADC process. (I recall spending
some time convincing a 'seat of the pants engineer' of this when his
design
wouldn't work. Even when he adopted the suggested changes he insisted
his
design would have worked if the ADC was more accurate. In fact, it would
have made it worse.)


No, Brian, I am not confused. It is a form of delta modulation, but is
used in an ADC. Two samples are taken, 2 or more times the sample rate
(i.e. if the sample rate were 20us, the first sample would be taken
every 20us, with the second sample following by 10us or less). The
difference is converted to a digital value for transmission. On the
other end, the reverse happens.

That is not what you have been describing. Now you are saying that the
ADC samples the amplitude of the signal just as I have been saying, but
now you are adding a step in which the delta is calculated which is what
I was describing with ADPCM (although I should have used the simpler and
more like your approach DPCM).


It is EXACTLY what I've been describing, but you're too stoopid to
understand it. But as usual, rather than trying to learn, you argue and
prove your stoopidity.

I have never heard of using it in the way you are describing though.
Even in DPCM the samples are taken at a fixed interval and the delta is
calculated on *every* pair of adjacent samples, not just every other. So
a sample stream of x0, x1, x2, x3, etc would produce delta values of d0,
d1, d2,... not just d0, d1...


That's OK. Those types of ADC's haven't heard of you, either, so I
guess you don't exist.

You describe two samples being taken for each data sample transmitted,
ignoring the change in signal between x1 and x2. The signal could not
be reconstructed with this data missing.


Once again you are proving you have no idea.


Yes, the signal can change by 1/2 lsb - but that's true of any ADC.

The sample and hold issue is a red herring and in fact, is counter
productive in a dual slope converter whose point is to average
(integrate) the signal over a period of time filtering higher frequency
content.


Which has nothing to do with what I'm discussing. But you have to
argue, anyway.


For any sufficiently high sample rate (i.e. 3x input signal or more),
this method is never less accurate than a simple voltage detecting ADC,
and in almost every case is more accurate. However, it is a more
complex circuit (on both ends), samples a much smaller analog value and
requires more exacting components and a higher cost (which is typically
the case for any circuit improvements).

The sampling method you describe is *not* different from a voltage
detecting ADC and therefore can't be better. All you are doing that is
different is the analog circuitry is obtaining the slope of the signal
over a short interval and is losing the slope of the signal between the
samples being ignored. Can you explain how it could be *more* accurate?


Once again you show you have no idea what I'm talking about, yet you
have to prove your stoopidity by arguing, anyway.

I suspect you are confusing the efficiency of the data rate with
accuracy. DPCM does provide some compression of the data rate when the
signal is over sampled as you seem to be describing. But it does
nothing to make the samples more accurate.


Once again you show you have no idea what I'm talking about, yet you
have to prove your stoopidity by arguing, anyway.


As I said - we studied them in one of my EE coursed back in the 70's. I
played with them for a while back then, but at the time the ICs were
pretty expensive for a college student.

Does this technique have a name? Any references?


Go to school, get an EE degree, then maybe we can talk about it
intelligently. I'm not wasting my time trying to teach the pig to sing.

Maybe - IF you were ever more interested in learning than arguing, I
would be more interested in discussing it with you. But you have
repeatedly proven that is not the case, so I'm not.

--
==================
Remove the "x" from my email address
Jerry, AI0K

==================

On 3/8/2015 4:37 PM, Jerry Stuckle wrote:
On 3/8/2015 2:39 PM, rickman wrote:
On 3/8/2015 9:03 AM, Jerry Stuckle wrote:
On 3/8/2015 7:35 AM, Brian Reay wrote:
Jeff wrote:

I will finally point out that your use of the term "slope detecting
ADC"
is invalid. Google returns exactly 4 hits when this term is entered
with quotes. The name of this converter may have slope in it, but
that
is because the circuit generates a slope, not because it is
detecting a
slope. Please look up the circuit and use a proper name for it
such as
integrating ADC or dual slope ADC. The integrating converter is
not at
all sensitive to the slope of the input signal, otherwise it would not
be able to measure a DC signal which has a slope of zero.

I'm only replying so that others are not confused by your
misstatements.



He is probably referring to a CVSD, otherwise known as a Delta
Modulator.

Jeff

I don't think so. In fact, I have to say Jerry seems a bit confused
in this
particular area, perhaps I have missed something.

ADC tend to have a sample and hold prior to the actual ADC convertor,
thus
the value converted is that at the beginning of the sample period OR if
another approach to conversion is used, you get some kind of average
over
the conversion period. (There are other techniques but those are the
main
ones.)

If you think about, a S/H is required if the rate of change of the input
signal means it can change by 1/2 lsb during the conversion time for
a SAR
ADC. This limits the overall BW of the ADC process. (I recall spending
some time convincing a 'seat of the pants engineer' of this when his
design
wouldn't work. Even when he adopted the suggested changes he insisted
his
design would have worked if the ADC was more accurate. In fact, it would
have made it worse.)


No, Brian, I am not confused. It is a form of delta modulation, but is
used in an ADC. Two samples are taken, 2 or more times the sample rate
(i.e. if the sample rate were 20us, the first sample would be taken
every 20us, with the second sample following by 10us or less). The
difference is converted to a digital value for transmission. On the
other end, the reverse happens.

That is not what you have been describing. Now you are saying that the
ADC samples the amplitude of the signal just as I have been saying, but
now you are adding a step in which the delta is calculated which is what
I was describing with ADPCM (although I should have used the simpler and
more like your approach DPCM).


It is EXACTLY what I've been describing, but you're too stoopid to
understand it. But as usual, rather than trying to learn, you argue and
prove your stoopidity.

I have never heard of using it in the way you are describing though.
Even in DPCM the samples are taken at a fixed interval and the delta is
calculated on *every* pair of adjacent samples, not just every other. So
a sample stream of x0, x1, x2, x3, etc would produce delta values of d0,
d1, d2,... not just d0, d1...


That's OK. Those types of ADC's haven't heard of you, either, so I
guess you don't exist.

You describe two samples being taken for each data sample transmitted,
ignoring the change in signal between x1 and x2. The signal could not
be reconstructed with this data missing.


Once again you are proving you have no idea.


Yes, the signal can change by 1/2 lsb - but that's true of any ADC.

The sample and hold issue is a red herring and in fact, is counter
productive in a dual slope converter whose point is to average
(integrate) the signal over a period of time filtering higher frequency
content.


Which has nothing to do with what I'm discussing. But you have to
argue, anyway.


For any sufficiently high sample rate (i.e. 3x input signal or more),
this method is never less accurate than a simple voltage detecting ADC,
and in almost every case is more accurate. However, it is a more
complex circuit (on both ends), samples a much smaller analog value and
requires more exacting components and a higher cost (which is typically
the case for any circuit improvements).

The sampling method you describe is *not* different from a voltage
detecting ADC and therefore can't be better. All you are doing that is
different is the analog circuitry is obtaining the slope of the signal
over a short interval and is losing the slope of the signal between the
samples being ignored. Can you explain how it could be *more* accurate?


Once again you show you have no idea what I'm talking about, yet you
have to prove your stoopidity by arguing, anyway.

I suspect you are confusing the efficiency of the data rate with
accuracy. DPCM does provide some compression of the data rate when the
signal is over sampled as you seem to be describing. But it does
nothing to make the samples more accurate.


Once again you show you have no idea what I'm talking about, yet you
have to prove your stoopidity by arguing, anyway.


As I said - we studied them in one of my EE coursed back in the 70's. I
played with them for a while back then, but at the time the ICs were
pretty expensive for a college student.

Does this technique have a name? Any references?


Go to school, get an EE degree, then maybe we can talk about it
intelligently. I'm not wasting my time trying to teach the pig to sing.

Maybe - IF you were ever more interested in learning than arguing, I
would be more interested in discussing it with you. But you have
repeatedly proven that is not the case, so I'm not.

Ok Jerry. I'm not going to argue with you. I asked you for the name of
this ADC technique and you can't come up with one. In this post *every*
single one of your replies is ad hominem rather than discussing the
issue. Clearly you have no basis for what you are saying. So there is
no point in trying to get you to explain any further.

--

Rick

In rec.radio.amateur.equipment rickman wrote:

snip

Ok Jerry. I'm not going to argue with you. I asked you for the name of
this ADC technique and you can't come up with one. In this post *every*
single one of your replies is ad hominem rather than discussing the
issue. Clearly you have no basis for what you are saying. So there is
no point in trying to get you to explain any further.

As will always happen if you dare to contradict the all-knowing and
mighty Stuckle.


--
Jim Pennino

On 3/8/2015 5:20 PM, rickman wrote:
On 3/8/2015 4:37 PM, Jerry Stuckle wrote:
On 3/8/2015 2:39 PM, rickman wrote:
On 3/8/2015 9:03 AM, Jerry Stuckle wrote:
On 3/8/2015 7:35 AM, Brian Reay wrote:
Jeff wrote:

I will finally point out that your use of the term "slope detecting
ADC"
is invalid. Google returns exactly 4 hits when this term is entered
with quotes. The name of this converter may have slope in it, but
that
is because the circuit generates a slope, not because it is
detecting a
slope. Please look up the circuit and use a proper name for it
such as
integrating ADC or dual slope ADC. The integrating converter is
not at
all sensitive to the slope of the input signal, otherwise it
would not
be able to measure a DC signal which has a slope of zero.

I'm only replying so that others are not confused by your
misstatements.



He is probably referring to a CVSD, otherwise known as a Delta
Modulator.

Jeff

I don't think so. In fact, I have to say Jerry seems a bit confused
in this
particular area, perhaps I have missed something.

ADC tend to have a sample and hold prior to the actual ADC convertor,
thus
the value converted is that at the beginning of the sample period
OR if
another approach to conversion is used, you get some kind of average
over
the conversion period. (There are other techniques but those are the
main
ones.)

If you think about, a S/H is required if the rate of change of the
input
signal means it can change by 1/2 lsb during the conversion time for
a SAR
ADC. This limits the overall BW of the ADC process. (I recall
spending
some time convincing a 'seat of the pants engineer' of this when his
design
wouldn't work. Even when he adopted the suggested changes he insisted
his
design would have worked if the ADC was more accurate. In fact, it
would
have made it worse.)


No, Brian, I am not confused. It is a form of delta modulation, but is
used in an ADC. Two samples are taken, 2 or more times the sample rate
(i.e. if the sample rate were 20us, the first sample would be taken
every 20us, with the second sample following by 10us or less). The
difference is converted to a digital value for transmission. On the
other end, the reverse happens.

That is not what you have been describing. Now you are saying that the
ADC samples the amplitude of the signal just as I have been saying, but
now you are adding a step in which the delta is calculated which is what
I was describing with ADPCM (although I should have used the simpler and
more like your approach DPCM).


It is EXACTLY what I've been describing, but you're too stoopid to
understand it. But as usual, rather than trying to learn, you argue and
prove your stoopidity.

I have never heard of using it in the way you are describing though.
Even in DPCM the samples are taken at a fixed interval and the delta is
calculated on *every* pair of adjacent samples, not just every other. So
a sample stream of x0, x1, x2, x3, etc would produce delta values of d0,
d1, d2,... not just d0, d1...


That's OK. Those types of ADC's haven't heard of you, either, so I
guess you don't exist.

You describe two samples being taken for each data sample transmitted,
ignoring the change in signal between x1 and x2. The signal could not
be reconstructed with this data missing.


Once again you are proving you have no idea.


Yes, the signal can change by 1/2 lsb - but that's true of any ADC.

The sample and hold issue is a red herring and in fact, is counter
productive in a dual slope converter whose point is to average
(integrate) the signal over a period of time filtering higher frequency
content.


Which has nothing to do with what I'm discussing. But you have to
argue, anyway.


For any sufficiently high sample rate (i.e. 3x input signal or more),
this method is never less accurate than a simple voltage detecting ADC,
and in almost every case is more accurate. However, it is a more
complex circuit (on both ends), samples a much smaller analog value and
requires more exacting components and a higher cost (which is typically
the case for any circuit improvements).

The sampling method you describe is *not* different from a voltage
detecting ADC and therefore can't be better. All you are doing that is
different is the analog circuitry is obtaining the slope of the signal
over a short interval and is losing the slope of the signal between the
samples being ignored. Can you explain how it could be *more* accurate?


Once again you show you have no idea what I'm talking about, yet you
have to prove your stoopidity by arguing, anyway.

I suspect you are confusing the efficiency of the data rate with
accuracy. DPCM does provide some compression of the data rate when the
signal is over sampled as you seem to be describing. But it does
nothing to make the samples more accurate.


Once again you show you have no idea what I'm talking about, yet you
have to prove your stoopidity by arguing, anyway.


As I said - we studied them in one of my EE coursed back in the
70's. I
played with them for a while back then, but at the time the ICs were
pretty expensive for a college student.

Does this technique have a name? Any references?


Go to school, get an EE degree, then maybe we can talk about it
intelligently. I'm not wasting my time trying to teach the pig to sing.

Maybe - IF you were ever more interested in learning than arguing, I
would be more interested in discussing it with you. But you have
repeatedly proven that is not the case, so I'm not.

Ok Jerry. I'm not going to argue with you. I asked you for the name of
this ADC technique and you can't come up with one. In this post *every*
single one of your replies is ad hominem rather than discussing the
issue. Clearly you have no basis for what you are saying. So there is
no point in trying to get you to explain any further.


You're right - I'm not answering your questions, because you have proven
yourself to be incapable of understanding even the simplest explanation.
The fact I WON'T answer you questions only means I refuse to try to
keep teaching the pig to sing - not that I don't know what I'm talking
about.

If you want to discuss this, get yourself an EE degree. Then just maybe
we can discuss technical topics intelligently.

Until then, you can continue to suck your pacifier.


--
==================
Remove the "x" from my email address
Jerry Stuckle

==================

On 08/03/15 19:58, rickman wrote:
On 3/8/2015 3:31 PM, Brian Reay wrote:
On 08/03/15 18:46, rickman wrote:
On 3/8/2015 9:53 AM, Brian Reay wrote:
Jerry Stuckle wrote:
On 3/8/2015 7:35 AM, Brian Reay wrote:
Jeff wrote:

I will finally point out that your use of the term "slope
detecting ADC"
is invalid. Google returns exactly 4 hits when this term is
entered
with quotes. The name of this converter may have slope in it, but
that
is because the circuit generates a slope, not because it is
detecting a
slope. Please look up the circuit and use a proper name for it
such as
integrating ADC or dual slope ADC. The integrating converter is
not at
all sensitive to the slope of the input signal, otherwise it would
not
be able to measure a DC signal which has a slope of zero.

I'm only replying so that others are not confused by your
misstatements.



He is probably referring to a CVSD, otherwise known as a Delta
Modulator.

Jeff

I don't think so. In fact, I have to say Jerry seems a bit confused
in this
particular area, perhaps I have missed something.

ADC tend to have a sample and hold prior to the actual ADC
convertor, thus
the value converted is that at the beginning of the sample period
OR if
another approach to conversion is used, you get some kind of average
over
the conversion period. (There are other techniques but those are the
main
ones.)

If you think about, a S/H is required if the rate of change of the
input
signal means it can change by 1/2 lsb during the conversion time for
a SAR
ADC. This limits the overall BW of the ADC process. (I recall
spending
some time convincing a 'seat of the pants engineer' of this when his
design
wouldn't work. Even when he adopted the suggested changes he
insisted his
design would have worked if the ADC was more accurate. In fact, it
would
have made it worse.)


No, Brian, I am not confused. It is a form of delta modulation,
but is
used in an ADC. Two samples are taken, 2 or more times the sample
rate
(i.e. if the sample rate were 20us, the first sample would be taken
every 20us, with the second sample following by 10us or less). The
difference is converted to a digital value for transmission. On the
other end, the reverse happens.

Yes, the signal can change by 1/2 lsb - but that's true of any ADC.

For any sufficiently high sample rate (i.e. 3x input signal or more),
this method is never less accurate than a simple voltage detecting
ADC,
and in almost every case is more accurate. However, it is a more
complex circuit (on both ends), samples a much smaller analog value
and
requires more exacting components and a higher cost (which is
typically
the case for any circuit improvements).

As I said - we studied them in one of my EE coursed back in the
70's. I
played with them for a while back then, but at the time the ICs were
pretty expensive for a college student.


Ok Jerry. You can, of course, find the rate of change (slope) by that
method if you know ( or assume) the signal is either only increasing or
decreasing between the samples. (A Nyquist matter).

However, the 1/2 lsb matter I mentioned is more for during the
conversion,
rather that for different samples. It is particularly important for
slower
ADC types, such as SAR implementations.

Can you explain your 1/2 lsb effect? What type of ADC are you referring
to? Different ADC types do require a S/H on the input for signals that
are not *highly* oversampled. For example a flash converter can mess up
and be quite a bit off if the signal is slewing during conversion. Same
with SAR converters. But I don't know of any effect where 1/2 lsb is a
threshold.

What threshold would you expect? As I recall, 1/2 lsb is the limit to
ensure that the conversion would be the 'same' over the conversion time.

I'm not sure what you mean by "the conversion would be the 'same' over
the conversion time", but I don't see how 1/2 lsb is any magic threshold.

If you are working with a flash converter, there are a number of
comparators each with a different threshold. The input signal could be
right at the edge of one of these thresholds so that a very tiny change
in the input signal will cause that threshold to be crossed during the
conversion.

Maybe I'm not understanding your point.

Sorry, I was referring to SAR converters. I should have been more precise.

With an SAR converter, if the signal changes during the conversion
period, then the converter will fail (at best)*, if the change is more
than 1/2 lsb. Therefore, the signal must remain constant (within 1/2
lsb) for the period of the conversion. If the maximum rate of change of
signal is known to be such that this will be the case, all is well, if
not, you need a sample and hold. You sample the signal, convert the
sample, and repeat the process for the next sample.

The S/H is designed to minimise the sampling time while ensuring the
required hold time is maintained- ie the sample stays within the
required 1/2 lsb for the conversion period.

Of course, some SAR ADCs have the S/H incorporated within the device,
others require either an external one or have provision for the C to be
external to permit design flexibility.


*by fail, rather depends on the converter. You will at least get an
false reading. I recall using one ADC which set a bit indicating a
failure to 'find' a 'match'.

I recall the details of the parameters of the S/H design being in the
application notes of the various ADCs I used over the years, I expect if
you look at some you can see for yourself.

By their nature (and application) flash converters don't require an S/H
but lack the resolution of SAR ADCs. They have other limitations of
course. If memory serves, one being that they are not monotonic which
was a requirement in the application I tended to apply ADCs (control
circuits, feedback loops don't like non-monotonic converters).

On 3/8/2015 6:06 PM, Brian Reay wrote:
On 08/03/15 19:58, rickman wrote:
On 3/8/2015 3:31 PM, Brian Reay wrote:
On 08/03/15 18:46, rickman wrote:
On 3/8/2015 9:53 AM, Brian Reay wrote:
Jerry Stuckle wrote:
On 3/8/2015 7:35 AM, Brian Reay wrote:
Jeff wrote:

I will finally point out that your use of the term "slope
detecting ADC"
is invalid. Google returns exactly 4 hits when this term is
entered
with quotes. The name of this converter may have slope in it, but
that
is because the circuit generates a slope, not because it is
detecting a
slope. Please look up the circuit and use a proper name for it
such as
integrating ADC or dual slope ADC. The integrating converter is
not at
all sensitive to the slope of the input signal, otherwise it would
not
be able to measure a DC signal which has a slope of zero.

I'm only replying so that others are not confused by your
misstatements.



He is probably referring to a CVSD, otherwise known as a Delta
Modulator.

Jeff

I don't think so. In fact, I have to say Jerry seems a bit confused
in this
particular area, perhaps I have missed something.

ADC tend to have a sample and hold prior to the actual ADC
convertor, thus
the value converted is that at the beginning of the sample period
OR if
another approach to conversion is used, you get some kind of average
over
the conversion period. (There are other techniques but those are the
main
ones.)

If you think about, a S/H is required if the rate of change of the
input
signal means it can change by 1/2 lsb during the conversion time for
a SAR
ADC. This limits the overall BW of the ADC process. (I recall
spending
some time convincing a 'seat of the pants engineer' of this when his
design
wouldn't work. Even when he adopted the suggested changes he
insisted his
design would have worked if the ADC was more accurate. In fact, it
would
have made it worse.)


No, Brian, I am not confused. It is a form of delta modulation,
but is
used in an ADC. Two samples are taken, 2 or more times the sample
rate
(i.e. if the sample rate were 20us, the first sample would be taken
every 20us, with the second sample following by 10us or less). The
difference is converted to a digital value for transmission. On the
other end, the reverse happens.

Yes, the signal can change by 1/2 lsb - but that's true of any ADC.

For any sufficiently high sample rate (i.e. 3x input signal or more),
this method is never less accurate than a simple voltage detecting
ADC,
and in almost every case is more accurate. However, it is a more
complex circuit (on both ends), samples a much smaller analog value
and
requires more exacting components and a higher cost (which is
typically
the case for any circuit improvements).

As I said - we studied them in one of my EE coursed back in the
70's. I
played with them for a while back then, but at the time the ICs were
pretty expensive for a college student.


Ok Jerry. You can, of course, find the rate of change (slope) by that
method if you know ( or assume) the signal is either only
increasing or
decreasing between the samples. (A Nyquist matter).

However, the 1/2 lsb matter I mentioned is more for during the
conversion,
rather that for different samples. It is particularly important for
slower
ADC types, such as SAR implementations.

Can you explain your 1/2 lsb effect? What type of ADC are you
referring
to? Different ADC types do require a S/H on the input for signals that
are not *highly* oversampled. For example a flash converter can
mess up
and be quite a bit off if the signal is slewing during conversion.
Same
with SAR converters. But I don't know of any effect where 1/2 lsb is a
threshold.

What threshold would you expect? As I recall, 1/2 lsb is the limit to
ensure that the conversion would be the 'same' over the conversion time.

I'm not sure what you mean by "the conversion would be the 'same' over
the conversion time", but I don't see how 1/2 lsb is any magic threshold.

If you are working with a flash converter, there are a number of
comparators each with a different threshold. The input signal could be
right at the edge of one of these thresholds so that a very tiny change
in the input signal will cause that threshold to be crossed during the
conversion.

Maybe I'm not understanding your point.

Sorry, I was referring to SAR converters. I should have been more precise.

With an SAR converter, if the signal changes during the conversion
period, then the converter will fail (at best)*, if the change is more
than 1/2 lsb. Therefore, the signal must remain constant (within 1/2
lsb) for the period of the conversion. If the maximum rate of change of
signal is known to be such that this will be the case, all is well, if
not, you need a sample and hold. You sample the signal, convert the
sample, and repeat the process for the next sample.

The S/H is designed to minimise the sampling time while ensuring the
required hold time is maintained- ie the sample stays within the
required 1/2 lsb for the conversion period.

Of course, some SAR ADCs have the S/H incorporated within the device,
others require either an external one or have provision for the C to be
external to permit design flexibility.

I understand what you are describing, but you still have not explained
the basis of the 1/2 lsb threshold. In an SAR converter the thresholds
are still fixed. So the amount of room for noise depends on the value
of the signal. If the signal is 1/4 of an lsb from the next conversion
threshold then 1/4 lsb of noise will cause a wrong reading. If the
signal is within 0.001 lsb of the threshold then 0.001 lsb of change in
the signal will cause an error.


*by fail, rather depends on the converter. You will at least get an
false reading. I recall using one ADC which set a bit indicating a
failure to 'find' a 'match'.

I recall the details of the parameters of the S/H design being in the
application notes of the various ADCs I used over the years, I expect if
you look at some you can see for yourself.

By their nature (and application) flash converters don't require an S/H
but lack the resolution of SAR ADCs. They have other limitations of
course. If memory serves, one being that they are not monotonic which
was a requirement in the application I tended to apply ADCs (control
circuits, feedback loops don't like non-monotonic converters).

Actually even flash converters work better with S/H in front of them. A
S/H circuit can have a very small aperture window while the converter
itself often has a much larger window. Remember that all of these
comparators work in parallel with different delays. Even if those
delays are small, these devices are designed to sample the fastest
signals possible and the variations can only be minimized, not
eliminated. So a slewing signal will not convert as accurately and can
cause the sort of error where the thermometer code output from the
comparators is not self consistent having more than one 0/1 transition
in the code. Some flash devices have circuitry to prevent this from
causing an output error, but it can add inaccuracy to the result.

--

Rick

On 3/8/2015 5:51 PM, Jerry Stuckle wrote:
On 3/8/2015 5:20 PM, rickman wrote:
On 3/8/2015 4:37 PM, Jerry Stuckle wrote:
On 3/8/2015 2:39 PM, rickman wrote:
On 3/8/2015 9:03 AM, Jerry Stuckle wrote:
On 3/8/2015 7:35 AM, Brian Reay wrote:
Jeff wrote:

I will finally point out that your use of the term "slope detecting
ADC"
is invalid. Google returns exactly 4 hits when this term is entered
with quotes. The name of this converter may have slope in it, but
that
is because the circuit generates a slope, not because it is
detecting a
slope. Please look up the circuit and use a proper name for it
such as
integrating ADC or dual slope ADC. The integrating converter is
not at
all sensitive to the slope of the input signal, otherwise it
would not
be able to measure a DC signal which has a slope of zero.

I'm only replying so that others are not confused by your
misstatements.



He is probably referring to a CVSD, otherwise known as a Delta
Modulator.

Jeff

I don't think so. In fact, I have to say Jerry seems a bit confused
in this
particular area, perhaps I have missed something.

ADC tend to have a sample and hold prior to the actual ADC convertor,
thus
the value converted is that at the beginning of the sample period
OR if
another approach to conversion is used, you get some kind of average
over
the conversion period. (There are other techniques but those are the
main
ones.)

If you think about, a S/H is required if the rate of change of the
input
signal means it can change by 1/2 lsb during the conversion time for
a SAR
ADC. This limits the overall BW of the ADC process. (I recall
spending
some time convincing a 'seat of the pants engineer' of this when his
design
wouldn't work. Even when he adopted the suggested changes he insisted
his
design would have worked if the ADC was more accurate. In fact, it
would
have made it worse.)


No, Brian, I am not confused. It is a form of delta modulation, but is
used in an ADC. Two samples are taken, 2 or more times the sample rate
(i.e. if the sample rate were 20us, the first sample would be taken
every 20us, with the second sample following by 10us or less). The
difference is converted to a digital value for transmission. On the
other end, the reverse happens.

That is not what you have been describing. Now you are saying that the
ADC samples the amplitude of the signal just as I have been saying, but
now you are adding a step in which the delta is calculated which is what
I was describing with ADPCM (although I should have used the simpler and
more like your approach DPCM).


It is EXACTLY what I've been describing, but you're too stoopid to
understand it. But as usual, rather than trying to learn, you argue and
prove your stoopidity.

I have never heard of using it in the way you are describing though.
Even in DPCM the samples are taken at a fixed interval and the delta is
calculated on *every* pair of adjacent samples, not just every other. So
a sample stream of x0, x1, x2, x3, etc would produce delta values of d0,
d1, d2,... not just d0, d1...


That's OK. Those types of ADC's haven't heard of you, either, so I
guess you don't exist.

You describe two samples being taken for each data sample transmitted,
ignoring the change in signal between x1 and x2. The signal could not
be reconstructed with this data missing.


Once again you are proving you have no idea.


Yes, the signal can change by 1/2 lsb - but that's true of any ADC.

The sample and hold issue is a red herring and in fact, is counter
productive in a dual slope converter whose point is to average
(integrate) the signal over a period of time filtering higher frequency
content.


Which has nothing to do with what I'm discussing. But you have to
argue, anyway.


For any sufficiently high sample rate (i.e. 3x input signal or more),
this method is never less accurate than a simple voltage detecting ADC,
and in almost every case is more accurate. However, it is a more
complex circuit (on both ends), samples a much smaller analog value and
requires more exacting components and a higher cost (which is typically
the case for any circuit improvements).

The sampling method you describe is *not* different from a voltage
detecting ADC and therefore can't be better. All you are doing that is
different is the analog circuitry is obtaining the slope of the signal
over a short interval and is losing the slope of the signal between the
samples being ignored. Can you explain how it could be *more* accurate?


Once again you show you have no idea what I'm talking about, yet you
have to prove your stoopidity by arguing, anyway.

I suspect you are confusing the efficiency of the data rate with
accuracy. DPCM does provide some compression of the data rate when the
signal is over sampled as you seem to be describing. But it does
nothing to make the samples more accurate.


Once again you show you have no idea what I'm talking about, yet you
have to prove your stoopidity by arguing, anyway.


As I said - we studied them in one of my EE coursed back in the
70's. I
played with them for a while back then, but at the time the ICs were
pretty expensive for a college student.

Does this technique have a name? Any references?


Go to school, get an EE degree, then maybe we can talk about it
intelligently. I'm not wasting my time trying to teach the pig to sing.

Maybe - IF you were ever more interested in learning than arguing, I
would be more interested in discussing it with you. But you have
repeatedly proven that is not the case, so I'm not.

Ok Jerry. I'm not going to argue with you. I asked you for the name of
this ADC technique and you can't come up with one. In this post *every*
single one of your replies is ad hominem rather than discussing the
issue. Clearly you have no basis for what you are saying. So there is
no point in trying to get you to explain any further.


You're right - I'm not answering your questions, because you have proven
yourself to be incapable of understanding even the simplest explanation.
The fact I WON'T answer you questions only means I refuse to try to
keep teaching the pig to sing - not that I don't know what I'm talking
about.

If you want to discuss this, get yourself an EE degree. Then just maybe
we can discuss technical topics intelligently.

Until then, you can continue to suck your pacifier.

My degree is from University of Maryland, an MSEE, 1981. But that is
irrelevant. My degree didn't teach me about how ADCs work. I learned
that from using them and reading every data book and app note I could
find over the years.

I'm still waiting for you to show me some sort of evidence that any ADC
converters work the way you describe.

--

Rick

On 3/8/2015 7:46 PM, rickman wrote:
On 3/8/2015 5:51 PM, Jerry Stuckle wrote:
On 3/8/2015 5:20 PM, rickman wrote:
On 3/8/2015 4:37 PM, Jerry Stuckle wrote:
On 3/8/2015 2:39 PM, rickman wrote:
On 3/8/2015 9:03 AM, Jerry Stuckle wrote:
On 3/8/2015 7:35 AM, Brian Reay wrote:
Jeff wrote:

I will finally point out that your use of the term "slope
detecting
ADC"
is invalid. Google returns exactly 4 hits when this term is
entered
with quotes. The name of this converter may have slope in it, but
that
is because the circuit generates a slope, not because it is
detecting a
slope. Please look up the circuit and use a proper name for it
such as
integrating ADC or dual slope ADC. The integrating converter is
not at
all sensitive to the slope of the input signal, otherwise it
would not
be able to measure a DC signal which has a slope of zero.

I'm only replying so that others are not confused by your
misstatements.



He is probably referring to a CVSD, otherwise known as a Delta
Modulator.

Jeff

I don't think so. In fact, I have to say Jerry seems a bit confused
in this
particular area, perhaps I have missed something.

ADC tend to have a sample and hold prior to the actual ADC
convertor,
thus
the value converted is that at the beginning of the sample period
OR if
another approach to conversion is used, you get some kind of average
over
the conversion period. (There are other techniques but those are the
main
ones.)

If you think about, a S/H is required if the rate of change of the
input
signal means it can change by 1/2 lsb during the conversion time for
a SAR
ADC. This limits the overall BW of the ADC process. (I recall
spending
some time convincing a 'seat of the pants engineer' of this when his
design
wouldn't work. Even when he adopted the suggested changes he
insisted
his
design would have worked if the ADC was more accurate. In fact, it
would
have made it worse.)


No, Brian, I am not confused. It is a form of delta modulation,
but is
used in an ADC. Two samples are taken, 2 or more times the sample
rate
(i.e. if the sample rate were 20us, the first sample would be taken
every 20us, with the second sample following by 10us or less). The
difference is converted to a digital value for transmission. On the
other end, the reverse happens.

That is not what you have been describing. Now you are saying that
the
ADC samples the amplitude of the signal just as I have been saying,
but
now you are adding a step in which the delta is calculated which is
what
I was describing with ADPCM (although I should have used the
simpler and
more like your approach DPCM).


It is EXACTLY what I've been describing, but you're too stoopid to
understand it. But as usual, rather than trying to learn, you argue
and
prove your stoopidity.

I have never heard of using it in the way you are describing though.
Even in DPCM the samples are taken at a fixed interval and the
delta is
calculated on *every* pair of adjacent samples, not just every
other. So
a sample stream of x0, x1, x2, x3, etc would produce delta values
of d0,
d1, d2,... not just d0, d1...


That's OK. Those types of ADC's haven't heard of you, either, so I
guess you don't exist.

You describe two samples being taken for each data sample transmitted,
ignoring the change in signal between x1 and x2. The signal could not
be reconstructed with this data missing.


Once again you are proving you have no idea.


Yes, the signal can change by 1/2 lsb - but that's true of any ADC.

The sample and hold issue is a red herring and in fact, is counter
productive in a dual slope converter whose point is to average
(integrate) the signal over a period of time filtering higher
frequency
content.


Which has nothing to do with what I'm discussing. But you have to
argue, anyway.


For any sufficiently high sample rate (i.e. 3x input signal or more),
this method is never less accurate than a simple voltage detecting
ADC,
and in almost every case is more accurate. However, it is a more
complex circuit (on both ends), samples a much smaller analog
value and
requires more exacting components and a higher cost (which is
typically
the case for any circuit improvements).

The sampling method you describe is *not* different from a voltage
detecting ADC and therefore can't be better. All you are doing
that is
different is the analog circuitry is obtaining the slope of the signal
over a short interval and is losing the slope of the signal between
the
samples being ignored. Can you explain how it could be *more*
accurate?


Once again you show you have no idea what I'm talking about, yet you
have to prove your stoopidity by arguing, anyway.

I suspect you are confusing the efficiency of the data rate with
accuracy. DPCM does provide some compression of the data rate when
the
signal is over sampled as you seem to be describing. But it does
nothing to make the samples more accurate.


Once again you show you have no idea what I'm talking about, yet you
have to prove your stoopidity by arguing, anyway.


As I said - we studied them in one of my EE coursed back in the
70's. I
played with them for a while back then, but at the time the ICs were
pretty expensive for a college student.

Does this technique have a name? Any references?


Go to school, get an EE degree, then maybe we can talk about it
intelligently. I'm not wasting my time trying to teach the pig to
sing.

Maybe - IF you were ever more interested in learning than arguing, I
would be more interested in discussing it with you. But you have
repeatedly proven that is not the case, so I'm not.

Ok Jerry. I'm not going to argue with you. I asked you for the name of
this ADC technique and you can't come up with one. In this post *every*
single one of your replies is ad hominem rather than discussing the
issue. Clearly you have no basis for what you are saying. So there is
no point in trying to get you to explain any further.


You're right - I'm not answering your questions, because you have proven
yourself to be incapable of understanding even the simplest explanation.
The fact I WON'T answer you questions only means I refuse to try to
keep teaching the pig to sing - not that I don't know what I'm talking
about.

If you want to discuss this, get yourself an EE degree. Then just maybe
we can discuss technical topics intelligently.

Until then, you can continue to suck your pacifier.

My degree is from University of Maryland, an MSEE, 1981. But that is
irrelevant. My degree didn't teach me about how ADCs work. I learned
that from using them and reading every data book and app note I could
find over the years.

I'm still waiting for you to show me some sort of evidence that any ADC
converters work the way you describe.


MSEE from University of Maryland? ROFLMAO!

I happen to live just a few miles from UMD. I know several graduates of
there, some of them EE's. And they know a lot more about EE than you
have shown. Including ADC's.

I have much more respect for UMD and its grads than that.

--
==================
Remove the "x" from my email address
Jerry, AI0K

==================