Tam/WB2TT wrote:
"Anthony Fremont" wrote in message

I have never seen clipping. These things are supposed to limit in
cutoff, not saturation. As the signal build up, the conduction angle
gets smaller and smaller until the device runs out of gain. That is
another way of saying that the DC value of the gate voltage gets more
negative the bigger the amplitude. This works out automatically with
a JFET. You need about 10K - 100K DC resistance from gate to ground.
Using a bipolar transistor is not a good idea.

I was wondering about the load that a bipolar would present. I will see if
I can find a JFET in my junk pile, thank you. :-)

Anthony Fremont wrote:

Pictures available in ABSE

The top trace (yellow) is taken between C4 and R2. The bottom trace
(cyan)
is taken at the base of the transistor. There is a switchercad file, but
the simulation will show allot of distortion that really isn't present in
the prototype circuit, because of lots of circuit capactance I suspect.
R1 was something I was playing with to try and tame the voltage across
L1/C3 being applied to the base.


Hello all,

I was tinkering with this LC oscillator (Colpitts/Clapp) this weekend. I
arrived at the values of C1 and C2 empirically after starting with a
crystal
oscillator circuit. The values in the original circuit created a horrid
waveform that looked allot like the simulation. After much tinkering
around and simulating, I come to the conclusion that getting a perfect
waveform is
nearly impossible, especially with big swing. It seems that the
transistor likes to take a bite out of the right half of the peak of the
wave.

What is the secret to beautiful waveforms? Do I need another LC resonator
on the output to fix it up? I mean, I'm getting a pretty nice wave now,
but there is still some distortion that you can just see at the top of the
peaks on the yellow trace.

How do you control the peak voltages of an LC resonattor without mangling
the waveform? The waveform at the junction of L1/C3 is of course quite
beautiful, how do I get it from there to the output? ;-)

I realize that I will need a buffer stage(s) before I can make any real
use of the signal, but I want the input to the buffer to be as perfect as
possible.

Thanks :-)

In some LC oscillators, the amplitude of the oscillation is controlled by a
feedback loop. For example, a rectifier can be used to create a DC voltage
proportional to the oscillation amplitude on the LC tank, and then an
op-amp can be used to compare the rectifier output signal to a reference
voltage. The output from the op-amp can be filtered and then used to
control the current in the oscillator core. It is difficult to do all of
this in a way that keeps the phase noise low, but given the right
simulation tools (e.g. SpectreRF which is rather expensive), good results
can be obtained. In particular, a well-defined oscillation amplitude can
help to keep the KVCO well controlled, which is useful in PLLs.

Chris

Helmut Sennewald wrote:
"Anthony Fremont" schrieb im Newsbeitrag
...
Helmut Sennewald wrote:
Hello Anthony,

1.
Please set the following option to sitch off data
reduction/compression in the result file..

.options plotwinsize=0

2.
You have to set a small maximum timestep in the .TRAN line too.
Maybe a value of 0.01*Period of oscillation if you hunt for very low
distortion.


Can you send me your file (.asc-file and model-file?) to check it?

In alt.binaries.schematics.electronic I have posted the schematic,
the asc-file and an oscilloscope screen shot from an actual circuit.
Here is the asc-file contents:


Hello Anthony,

The large capacitance of C1 (10nF) has caused an interrupted
oscillation. Please change its value to 1000p and the oscillator will
work as expected. I have also added MEASURE-commands to measure the
frequency. View - SPICE Error Log

Another method is using the FFT in the waveform viewer.

Best regards,
Helmut

Save as "osc1.asc".

Version 4
SHEET 1 880 708
WIRE -688 -96 -784 -96
WIRE -576 -96 -688 -96
WIRE -304 -96 -576 -96
WIRE -784 -64 -784 -96
WIRE -688 -64 -688 -96
WIRE -576 -16 -576 -96
WIRE -304 32 -304 -96
WIRE -784 48 -784 16
WIRE -688 48 -688 0
WIRE -576 80 -576 64
WIRE -480 80 -576 80
WIRE -432 80 -480 80
WIRE -368 80 -432 80
WIRE -576 128 -576 80
WIRE -432 144 -432 80
WIRE -576 240 -576 208
WIRE -432 240 -432 208
WIRE -304 240 -304 128
WIRE -304 240 -432 240
WIRE -240 240 -304 240
WIRE -160 240 -240 240
WIRE -64 240 -96 240
WIRE -32 240 -64 240
WIRE -576 272 -576 240
WIRE -432 272 -432 240
WIRE -32 272 -32 240
WIRE -304 288 -304 240
WIRE -32 368 -32 352
WIRE -576 384 -576 336
WIRE -432 384 -432 336
WIRE -432 384 -576 384
WIRE -304 384 -304 368
WIRE -304 384 -432 384
WIRE -432 416 -432 384
FLAG -784 48 0
FLAG -432 416 0
FLAG -688 48 0
FLAG -32 368 0
FLAG -64 240 out
FLAG -240 240 e
FLAG -480 80 b
FLAG -576 240 lc
SYMBOL voltage -784 -80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5.8
SYMBOL res -592 -32 R0
SYMATTR InstName R3
SYMATTR Value 100k
SYMBOL npn -368 32 R0
SYMATTR InstName Q3
SYMATTR Value 2N3904
SYMBOL cap -448 144 R0
SYMATTR InstName C1
SYMATTR Value 1000p
SYMBOL res -320 272 R0
SYMATTR InstName R7
SYMATTR Value 1k
SYMBOL cap -448 272 R0
SYMATTR InstName C2
SYMATTR Value 500p
SYMBOL ind -592 112 R0
WINDOW 39 36 108 Left 0
SYMATTR InstName L1
SYMATTR Value 20µ
SYMATTR SpiceLine Rser=.1
SYMBOL cap -592 272 R0
SYMATTR InstName C3
SYMATTR Value 200p
SYMBOL cap -96 224 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C4
SYMATTR Value 270p
SYMBOL cap -704 -64 R0
SYMATTR InstName C5
SYMATTR Value 10µ
SYMBOL res -48 256 R0
SYMATTR InstName R2
SYMATTR Value 100k
TEXT -824 -152 Left 0 !.tran 0 200uS 0 4n
TEXT -824 -184 Left 0 !.options plotwinsize=0
TEXT -816 472 Left 0 !.measure tran t1 FIND time WHEN V(out)=0 TD=90u
RISE=1 TEXT -816 504 Left 0 !.measure tran t2 FIND time WHEN V(out)=0
TD=90u RISE=101
TEXT -816 536 Left 0 !.measure tran f0 PARAM 100/(t2-t1)
TEXT -816 576 Left 0 ;View - SPICE Error Log \nfor the measured
frequency TEXT -520 -184 Left 0 ;C1 changed to 1000p!

Thank you very much. :-) I have now switched to using an MPF102 JFET
instead of the bipolar and much less capacitance for C1 (now 470pF). I only
get a 2V peak to peak signal out now, but it's quite nice looking.

Tim Wescott wrote:
Anthony Fremont wrote:

Some material I read suggested keeping Xl of L1 at ~300Ohms, the
series Xc (C3) at ~200Ohms and Xc of C1/C2 at 45Ohms. Do you have
any thoughts on that? Right now I have way too much inductance for
3.5MHz by that theory, and judging from other circuits I've seen.
10uH seems to be the going thing for around 4MHz?


That sounds more or less right. With a Clapp oscillator the main tank
is isolated by the series cap, so more of the energy is kept in the
coil and C3, and less of it shows up in C1, C2, and the transistor.

If you're driving a balanced mixer you want to have an LO signal that
doesn't have much even-harmonic (2nd, 4th, etc.) energy in it, but
for a casual receiver that's the least of your worries. Since you're
operating at a fixed frequency it may be a good idea to just feed the
oscillator output into a single-tuned resonant circuit to clean it up,
then send it on to the mixer.

Ok, I've now put in an MPF102 and changed R3 to a pull-down. I lowered C1
to 470pF and I get a nifty 2V p-p sine wave on the output. It really tamed
the tank circuit voltage down as well. Which brings up a question, with the
tank now completely DC blocked from Vcc and Vss, where does it get it's
energy. I assume that it must come thru the gate. How does that happen?
:-? My circuit is much like Figure 1 here, without the diode though:
http://www.electronics-tutorials.com...scillators.htm

"Anthony Fremont" wrote in message
...
Pictures available in ABSE

The top trace (yellow) is taken between C4 and R2. The bottom trace
(cyan)
is taken at the base of the transistor. There is a switchercad file, but
the simulation will show allot of distortion that really isn't present in
the prototype circuit, because of lots of circuit capactance I suspect.
R1
was something I was playing with to try and tame the voltage across L1/C3
being applied to the base.


Hello all,

I was tinkering with this LC oscillator (Colpitts/Clapp) this weekend. I
arrived at the values of C1 and C2 empirically after starting with a
crystal
oscillator circuit. The values in the original circuit created a horrid
waveform that looked allot like the simulation. After much tinkering
around
and simulating, I come to the conclusion that getting a perfect waveform
is
nearly impossible, especially with big swing. It seems that the
transistor
likes to take a bite out of the right half of the peak of the wave.

What is the secret to beautiful waveforms? Do I need another LC resonator
on the output to fix it up? I mean, I'm getting a pretty nice wave now,
but
there is still some distortion that you can just see at the top of the
peaks
on the yellow trace.

How do you control the peak voltages of an LC resonattor without mangling
the waveform? The waveform at the junction of L1/C3 is of course quite
beautiful, how do I get it from there to the output? ;-)

I realize that I will need a buffer stage(s) before I can make any real
use
of the signal, but I want the input to the buffer to be as perfect as
possible.

Thanks :-)

The prettiest waveforms come from balanced oscillators. Distortion then
turns up as 3rd 5th 7th etc harmonics which are far less ugly than the 2nd
3rd 4th 5th etc generated by the single ended types. Balanced ALC is also
easier and more effective.
My own experience says that 'prettier' is better. Those oscillators offering
gross distorted outputs also seem to suffer badly in other areas and gross
distortion always causes problems further down the line.
Procuring good quality is a classic black art, one aspect is to allow the
LC just an occasional vague glimpse of the maintaining amplifier. Another is
to cause limiting by use of an amp having a gentle gain change (eg Fet v
bipolar) and the other is ALC. (Or all three together).
Failing that, there is always the cop-out of an output filter
john



--
Posted via a free Usenet account from http://www.teranews.com

Anthony Fremont wrote:
Tim Wescott wrote:

Anthony Fremont wrote:


Some material I read suggested keeping Xl of L1 at ~300Ohms, the
series Xc (C3) at ~200Ohms and Xc of C1/C2 at 45Ohms. Do you have
any thoughts on that? Right now I have way too much inductance for
3.5MHz by that theory, and judging from other circuits I've seen.
10uH seems to be the going thing for around 4MHz?



That sounds more or less right. With a Clapp oscillator the main tank
is isolated by the series cap, so more of the energy is kept in the
coil and C3, and less of it shows up in C1, C2, and the transistor.

If you're driving a balanced mixer you want to have an LO signal that
doesn't have much even-harmonic (2nd, 4th, etc.) energy in it, but
for a casual receiver that's the least of your worries. Since you're
operating at a fixed frequency it may be a good idea to just feed the
oscillator output into a single-tuned resonant circuit to clean it up,
then send it on to the mixer.


Ok, I've now put in an MPF102 and changed R3 to a pull-down. I lowered C1
to 470pF and I get a nifty 2V p-p sine wave on the output. It really tamed
the tank circuit voltage down as well. Which brings up a question, with the
tank now completely DC blocked from Vcc and Vss, where does it get it's
energy. I assume that it must come thru the gate. How does that happen?
:-? My circuit is much like Figure 1 here, without the diode though:
http://www.electronics-tutorials.com...scillators.htm


It comes from the source, through the coupling capacitors -- Cfb-a and
Cfb-b in your link.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Posting from Google? See http://cfaj.freeshell.org/google/

"Applied Control Theory for Embedded Systems" came out in April.
See details at http://www.wescottdesign.com/actfes/actfes.html

Tam/WB2TT wrote:

I have never seen clipping. These things are supposed to limit in
cutoff, not saturation. As the signal build up, the conduction angle
gets smaller and smaller until the device runs out of gain. That is
another way of saying that the DC value of the gate voltage gets more
negative the bigger the amplitude. This works out automatically with
a JFET. You need about 10K - 100K DC resistance from gate to ground.
Using a bipolar transistor is not a good idea.

I have now changed it to an MPF102 that I've had laying around for many
years. It works great, thanks.
:-)

"Anthony Fremont" wrote in message
...
Tam/WB2TT wrote:

I have never seen clipping. These things are supposed to limit in
cutoff, not saturation. As the signal build up, the conduction angle
gets smaller and smaller until the device runs out of gain. That is
another way of saying that the DC value of the gate voltage gets more
negative the bigger the amplitude. This works out automatically with
a JFET. You need about 10K - 100K DC resistance from gate to ground.
Using a bipolar transistor is not a good idea.

I have now changed it to an MPF102 that I've had laying around for many
years. It works great, thanks.
:-)

Glad it worked out. By the way the feedback path is through the capacitive
network between source and gate. That would be more obvious in the
configuration that uses a tapped inductor, but works the same way. Leaving
out the diode was the right thing to do; it just adds to the noise. I don't
know what kind of stability and linearity you need, but if that is
important, do not use the common type of ceramic capacitors that are meant
for bypassing. They are lossy, and their value varies with applied voltage.
Use mica, NPO ceramic, or Mylar and similar for larger values.

Tam

On Mon, 19 Mar 2007 16:25:26 -0500, "Anthony Fremont"
wrote:

Tam/WB2TT wrote:
"Anthony Fremont" wrote in message

I have never seen clipping. These things are supposed to limit in
cutoff, not saturation. As the signal build up, the conduction angle
gets smaller and smaller until the device runs out of gain. That is
another way of saying that the DC value of the gate voltage gets more
negative the bigger the amplitude. This works out automatically with
a JFET. You need about 10K - 100K DC resistance from gate to ground.
Using a bipolar transistor is not a good idea.

I was wondering about the load that a bipolar would present. I will see if
I can find a JFET in my junk pile, thank you. :-)

Without going to the purity levels that Tom requires, I've always found that
bipolars can be used to produce a fairly reasonable "visibly sinusoidal" (see
note) waveform. Follow the oscillator with an amplifier stage which drives a
limiter/clipper, and use that to control a gain element in the oscillator. It's
like the incandescent non-linearity arrangement except the oscillator stage
waveform remains fairly clean.

(Note: Harmonic distortion not readily discernible on a CRO)

Tam/WB2TT wrote:
"Anthony Fremont" wrote in message

I have now changed it to an MPF102 that I've had laying around for
many years. It works great, thanks.
:-)

Glad it worked out. By the way the feedback path is through the
capacitive network between source and gate. That would be more
obvious in the configuration that uses a tapped inductor, but works

I had to play around with this quite a bit to get it running near 10MHz. It
seemed to be more picky about the cap ratios than their actual values.

the same way. Leaving out the diode was the right thing to do; it
just adds to the noise. I don't know what kind of stability and

I figured that it would cause horrid clipping the way it was installed. I
thought maybe the designer intended it to be the other way around to protect
the transistor from reverse voltages on the gate, hmm.... always something
to keep you guessing. ;-)

linearity you need, but if that is important, do not use the common
type of ceramic capacitors that are meant for bypassing. They are
lossy, and their value varies with applied voltage. Use mica, NPO
ceramic, or Mylar and similar for larger values.

I don't really "need" anything in particular, it's just an exercise to try
and learn something. I just used the ceramic caps because they were handy.
I didn't have a pile of NPO caps laying around. ;-) I d

Time to add a buffer now since the scope probes load it down so badly now.
I'm getting 1.1Vpp into the apparent 5M load of two scope probes. It's
probably pulled a ton off frequency as well. Let's see.....(removes one
probe).....yep, 90KHz rise in frequency after taking one probe off.