On Aug 19, 5:12 pm, ken scharf wrote:
Gian, I7SWX wrote:
Now we have to find a low phase clock generator around 1.0 to 1.3 GHz.

73

Gian
I7SWX

Rots a Ruck!
From the early specs looked like the chip has a built in PLL to
generate the clock from a lower frequency source. Phase noise might not
be as good though.

For applications sensitive to phase noise, the built in PLL's are not
a help but a pretty severe hindrance. 27 dB of hindrance in particular
for the chips I'm familiar with (AD9954 family) for phase noise 1kHz
out.

That doesn't mean that the DDS's (using refclock PLL or not) aren't
still damn useful for all sorts of stuff!

Tim.