On Aug 20, 7:43 pm, Tim Shoppa wrote:
On Aug 19, 5:12 pm, ken scharf wrote:

Gian, I7SWX wrote:
Now we have to find a low phase clock generator around 1.0 to 1.3 GHz.

73

Gian
I7SWX

Rots a Ruck!
From the early specs looked like the chip has a built in PLL to
generate the clock from a lower frequency source. Phase noise might not
be as good though.

For applications sensitive to phase noise, the built in PLL's are not
a help but a pretty severe hindrance. 27 dB of hindrance in particular
for the chips I'm familiar with (AD9954 family) for phase noise 1kHz
out.

That doesn't mean that the DDS's (using refclock PLL or not) aren't
still damn useful for all sorts of stuff!

Tim.

Hi Ken,

Tim did comment properly to your PLL question.

User has to decide what he needs and if his application will be OK
with the internal PLL multiplier or need an external low noise clock.

If one live in a place where the roads are not good he hs to
compromise ... probably it is not good he buys a Ferrari but could be
OK with a Corvette...maybe red...

If you have a high performance RX front-end probably it is better to
use an AD9912 and an external Low noise oscillatorgiving at least 1Ghz
clean signal for low phase noise and low spurs. If you have a SoftRock
SDR I am sure you will be OK with an AD9851 using the internal PLL
like it is done in the DDS-60.

73

Gian
I7SWX