I thought I would cross post this to rec.radio.amateur.moderated. They
have made a number of announcements about this and seem to be
encouraging the practice.

Rick


On 12/19/2012 3:51 PM, rickman wrote:
On 12/19/2012 10:26 AM, garyr wrote:

I don't understand how you intend to use an LVDS input for the WWVB
signal?
Could you explain.

I guess you didn't read my initial post. My intent is to create an
all-digital receiver at very low power. The receiver ICs around use
standard analog technology to detect the AM signal. WWVB has added phase
modulation which should be receivable at a lower SNR. I also want to
detect both modulation schemes and compare the results.


Have you considered using a WWVB receiver IC? I don't know what kind of
power they require but they generate the 1pps PWM signal which could be
processed by a low-power microprocessor very easily.

They are fairly low power as can be CPU chips when cycled on and off as
needed. But I want to do this in an FPGA so I can see just how low power
it can be.


http://www.c-max-time.com/products/showProduct.php?id=2
http://www.pvelectronics.co.uk/index...&products_id=7

http://www.ntp-time-server.com/wwvb-...b-receiver.htm

I've constructed loop antennas using both RG-58 (60 KHz) and RG-6, or
something similar to RG-6 (~20 KHz) and had good luck with both. I
haven't
compared the outputs of both tuned to 60 KHz so I can't say much about
how
their electrical performance compare. The RG-6 with the aluminum
shield is a
PITA
because you can't make a solder connection to it. Self-resonance will
not be
a problem. 100' of RG-58 on a 1 meter dia. frame required about 25 nF to
resonate at 60 KHz. One advantage of the febo-type antenna with the
1-turn
pickup loop is that its output impedance is very low which means that the
antenna can be located away from the receiver.

The cable I have already has F type connectors on the ends, so I don't
care about the aluminum shield. I did have to shop around a bit to find
one with an all copper inner conductor. Seems they use copper coated
steel for CATV. I think my numbers are for a bit less than 80 nF of
capacitance so I bought a bunch of 15 nF silver mica parts and some
other small values to tune it in closely, then I have a triple bank,
0-500 pF tuner cap from an old receiver for final tuning. Once I have
the rest of the system working well, I'll likely use fixed values of
caps to tune the antenna without the variable cap. I saw one antenna
that used a bank of roughly power of 2 caps with switches to allow the
antenna to be tuned easily, cute.

I am thinking of using a ferrite core as a coupling transformer as it
will give me a lot of voltage gain. I am looking to get towards 10,000
gain from combined Q and transformer.

The LVDS input on the FPGA will act as a 1 bit ADC. I was planning to
use this in a Sigma-Delta converter and produce a 4 bit value at 240 kHz
(4x carrier rate). I'm not sure I need the Sigma-Delta converter and
might end up just using the 1 bit from the LVDS directly. By
downconverting to DC and downsampling to 30 Hz I will get a *lot* of
processing gain with an SNR improvement of some 33 dB (assuming
uncorrelated noise). Another way to look at the digital design is as a
very long FIR filter resulting in a filter with a very narrow bandpass
or one bin of a DFT. Turns out they are all the same math in this case
(multiply by 1, 0, -1, 0 sequence).

There are a few wrinkles I haven't figured out yet. I need a sample
clock that is both accurate and low power. I have yet to find that. XO
oscillators I have found over 1 MHz are all in the mA range. I'm
thinking of using the very poor internal oscillator in the FPGA and
calibrating it to a 32.768 kHz reference which can be both accurate and
low power. But I don't yet know if the internal oscillator is low power
enough. I need to fire up the eval board (gratis from NuHorizons) and
measure the power consumption with and without the internal oscillator
enabled. If the power consumption is low enough I can frequency lock it
to the clock oscillator and come up with a calibration factor. Then the
sample clock can be generated internally using a DCO updated with each
calibration.

Thanks for discussing this with me. I like to bounce ideas off of other
people.

Rick