Hoping someone here either can tell me this or knows a better group at
which to find the answer...

Say I have this FET whose optimal match for noise is, let's say, 300+j30
but I'm willing to match it out at e.g. 90+j17 for a decent noise/gain
trade-off.

The data sheet for this FET (ATF-54143, an enhancement-mode JFET of all
things) recommends a series-cap, shunt-L which also serves for biasing.

I have seen a few examples of this in various write-ups but I'm a little
confused about which way to work it on the smith chart, Zo to Zs, or the
other way.

In the above example if I were working starting at Zo which is 50 ohms
in this case for simplicity, I'd add enough XC to drag it down to the
right admittance circle, then add enough YL to drag it back up to the
chosen match point. The capacitance and inductance I come up with
don't match the ones in the examples I've seen, so I'm a bit puzzled.

Thanks for whatever anyone can tell me on this.