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#11
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Hi,
Have a look at the 74HCT40103 on the Philips site. Although the output is asymmetric, it will divide by any number between 2 and 255. Cheers - Joe |
#12
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In article , Paul Keinanen
writes: On Tue, 18 Nov 2003 01:27:56 GMT, (J M Noeding) wrote: for my quite unstable counters I've got some 0.1ppm 9.6MHz VCXO's (guaranteed over temperature range -20...+20°C), the problem is that the original XO is 1MHz with 7490 divider, and now I need a divide by 96 downcounter. The VCXO drives a 74LS14, so it shouldn't be any fan out problem, but I am not aware what is the readily available divider to choose. The counter is mentioned on http://home.online.no/~la8ak/m21.htm , but it is Norwegian text Isn't the 74(LS)92 divide by 12 counter available anymore ? With an addition of a 74(LS)93 divide by 16 counter (divide by 192 total), you can get the required divide by 96 ratio, if you skip the independent divide by 2 section from either the '92 or '93. If you can not get the '92, get two '93 chips, let the first divide by 16 down to 600 kHz. Using only the divide by 8 part of the second '93, detect the "6" count with a two input AND/NAND gate and reset the counter. IIRC, the '93 contains a built in two input NAND gate in the reset circuit, so these inputs needs only be connected to the two most significant outputs of the divide by 8 counter. The required 100 kHz output can be taken from the most significant output (it has a 66:33 output ratio). If you need 50:50 ratio, first divide by 8 in the first '93, then by 6 in the second '93 and then by two in the independent section in the first '93. An alternate is to use a chain of presettable binary or decade counters such as the 74HC160 or 74HC190 families. Or use 74F series to assure high speed... Since you have a need to divide by 96, a 7-stage binary chain that would normally divide by 128 can be preset to a state of 32 at the end of the count. The count chain then goes through 96 states before reaching the end of the count again...which can initiate the preset. [all the other stages not preset would be tied to ground] The 8th stage would simply be unused Initiating the preset pulse can be a simple C-R coupling to get about a 40 nanoSecond spike at the end of the count. If you think you need it, you can use a spare inverter or a single bipolar to couple the end-of-count transition spike into the Load pins. With the 190 family you get a choice of Up or Down counting to ease your arithmetic...which can be adapted to the division control lines if there are a lot of different states selected. I'd recommend synchronous counter ICs running at 9.6 MHz. With the 190 series the input loading is only two gate inputs for parallel synchronism using two binary ICs. Same with the Parallel Load line. Internal chip buffering handles those. Only two 16-pin DIPs needed to do the job. Some of the older datasheets have example circuitry for preset counting. The 160 and 190 families have been around for a few decades, are still used in new designs and still available. Len Anderson retired (from regular hours) electronic engineer person |
#13
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In article , Paul Keinanen
writes: On Tue, 18 Nov 2003 01:27:56 GMT, (J M Noeding) wrote: for my quite unstable counters I've got some 0.1ppm 9.6MHz VCXO's (guaranteed over temperature range -20...+20°C), the problem is that the original XO is 1MHz with 7490 divider, and now I need a divide by 96 downcounter. The VCXO drives a 74LS14, so it shouldn't be any fan out problem, but I am not aware what is the readily available divider to choose. The counter is mentioned on http://home.online.no/~la8ak/m21.htm , but it is Norwegian text Isn't the 74(LS)92 divide by 12 counter available anymore ? With an addition of a 74(LS)93 divide by 16 counter (divide by 192 total), you can get the required divide by 96 ratio, if you skip the independent divide by 2 section from either the '92 or '93. If you can not get the '92, get two '93 chips, let the first divide by 16 down to 600 kHz. Using only the divide by 8 part of the second '93, detect the "6" count with a two input AND/NAND gate and reset the counter. IIRC, the '93 contains a built in two input NAND gate in the reset circuit, so these inputs needs only be connected to the two most significant outputs of the divide by 8 counter. The required 100 kHz output can be taken from the most significant output (it has a 66:33 output ratio). If you need 50:50 ratio, first divide by 8 in the first '93, then by 6 in the second '93 and then by two in the independent section in the first '93. An alternate is to use a chain of presettable binary or decade counters such as the 74HC160 or 74HC190 families. Or use 74F series to assure high speed... Since you have a need to divide by 96, a 7-stage binary chain that would normally divide by 128 can be preset to a state of 32 at the end of the count. The count chain then goes through 96 states before reaching the end of the count again...which can initiate the preset. [all the other stages not preset would be tied to ground] The 8th stage would simply be unused Initiating the preset pulse can be a simple C-R coupling to get about a 40 nanoSecond spike at the end of the count. If you think you need it, you can use a spare inverter or a single bipolar to couple the end-of-count transition spike into the Load pins. With the 190 family you get a choice of Up or Down counting to ease your arithmetic...which can be adapted to the division control lines if there are a lot of different states selected. I'd recommend synchronous counter ICs running at 9.6 MHz. With the 190 series the input loading is only two gate inputs for parallel synchronism using two binary ICs. Same with the Parallel Load line. Internal chip buffering handles those. Only two 16-pin DIPs needed to do the job. Some of the older datasheets have example circuitry for preset counting. The 160 and 190 families have been around for a few decades, are still used in new designs and still available. Len Anderson retired (from regular hours) electronic engineer person |
#14
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On Tue, 18 Nov 2003 01:27:56 GMT, (J M Noeding) wrote: for my quite unstable counters I've got some 0.1ppm 9.6MHz VCXO's (guaranteed over temperature range -20...+20°C), the problem is that the original XO is 1MHz with 7490 divider, and now I need a divide by 96 downcounter. The VCXO drives a 74LS14, so it shouldn't be any fan out problem, but I am not aware what is the readily available divider to choose. I really should have remembered the 74HC40103 presetable divider - I designed one into a circuit just a few years ago..... There is a fairly similar 40102. My suggestion of the 74HC4059 was overkill by a hard-to-get part. |
#15
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On Tue, 18 Nov 2003 01:27:56 GMT, (J M Noeding) wrote: for my quite unstable counters I've got some 0.1ppm 9.6MHz VCXO's (guaranteed over temperature range -20...+20°C), the problem is that the original XO is 1MHz with 7490 divider, and now I need a divide by 96 downcounter. The VCXO drives a 74LS14, so it shouldn't be any fan out problem, but I am not aware what is the readily available divider to choose. I really should have remembered the 74HC40103 presetable divider - I designed one into a circuit just a few years ago..... There is a fairly similar 40102. My suggestion of the 74HC4059 was overkill by a hard-to-get part. |
#16
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On Tue, 18 Nov 2003 09:40:59 +0000 (UTC), Joe McElvenney
wrote: Hi, Have a look at the 74HCT40103 on the Philips site. Although the output is asymmetric, it will divide by any number between 2 and 255. Cheers - Joe Thanks for the suggestion, I've used CMOS for almost 30 years and only use TTL when it is no other solution, one such device is with the 7493 as OH3LWR mention (believe it could divided by some strange factor, too). problem is that I have hundreds of standard CMOS devices and they usually (except Philips devices) goes near 10MHz. The reason for choosing a down counter is to avoid asymmetrical output signal which might upset the counter if the oscillatorboard has some distance from the old dividers, but is still some 7490's left in the chain. 73 Jan-Martin, LA8AK http://home.online.no/~la8ak/29a.htm -- remove ,xnd to reply (Spam precaution!) |
#17
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On Tue, 18 Nov 2003 09:40:59 +0000 (UTC), Joe McElvenney
wrote: Hi, Have a look at the 74HCT40103 on the Philips site. Although the output is asymmetric, it will divide by any number between 2 and 255. Cheers - Joe Thanks for the suggestion, I've used CMOS for almost 30 years and only use TTL when it is no other solution, one such device is with the 7493 as OH3LWR mention (believe it could divided by some strange factor, too). problem is that I have hundreds of standard CMOS devices and they usually (except Philips devices) goes near 10MHz. The reason for choosing a down counter is to avoid asymmetrical output signal which might upset the counter if the oscillatorboard has some distance from the old dividers, but is still some 7490's left in the chain. 73 Jan-Martin, LA8AK http://home.online.no/~la8ak/29a.htm -- remove ,xnd to reply (Spam precaution!) |
#18
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In article , wrote:
Hi for my quite unstable counters I've got some 0.1ppm 9.6MHz VCXO's (guaranteed over temperature range -20...+20°C), the problem is that the original XO is 1MHz with 7490 divider, and now I need a divide by 96 downcounter. The VCXO drives a 74LS14, so it shouldn't be any fan out problem, but I am not aware what is the readily available divider to choose. The counter is mentioned on http://home.online.no/~la8ak/m21.htm , but it is Norwegian text hpe 2 hr fm u 73 Jan-Martin, LA8AK http://home.online.no/~la8ak/d.htm You can make a ÷3 out of a couple of J-K flip-flops, then use that to clock a 5 stage binary counter. That way you get 50% duty cycle square waves at 1.6 MHz, 800 kHz, etc. all the way down. Just a suggestion -- there are many other ways. Dr. G. |
#19
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In article , wrote:
Hi for my quite unstable counters I've got some 0.1ppm 9.6MHz VCXO's (guaranteed over temperature range -20...+20°C), the problem is that the original XO is 1MHz with 7490 divider, and now I need a divide by 96 downcounter. The VCXO drives a 74LS14, so it shouldn't be any fan out problem, but I am not aware what is the readily available divider to choose. The counter is mentioned on http://home.online.no/~la8ak/m21.htm , but it is Norwegian text hpe 2 hr fm u 73 Jan-Martin, LA8AK http://home.online.no/~la8ak/d.htm You can make a ÷3 out of a couple of J-K flip-flops, then use that to clock a 5 stage binary counter. That way you get 50% duty cycle square waves at 1.6 MHz, 800 kHz, etc. all the way down. Just a suggestion -- there are many other ways. Dr. G. |