In article , Paul Keinanen
writes:

On Tue, 18 Nov 2003 01:27:56 GMT, (J M Noeding)
wrote:

for my quite unstable counters I've got some 0.1ppm 9.6MHz VCXO's
(guaranteed over temperature range -20...+20°C), the problem is that
the original XO is 1MHz with 7490 divider, and now I need a divide by
96 downcounter. The VCXO drives a 74LS14, so it shouldn't be any fan
out problem, but I am not aware what is the readily available divider
to choose. The counter is mentioned on
http://home.online.no/~la8ak/m21.htm , but it is Norwegian text

Isn't the 74(LS)92 divide by 12 counter available anymore ? With an
addition of a 74(LS)93 divide by 16 counter (divide by 192 total), you
can get the required divide by 96 ratio, if you skip the independent
divide by 2 section from either the '92 or '93.

If you can not get the '92, get two '93 chips, let the first divide by
16 down to 600 kHz. Using only the divide by 8 part of the second '93,
detect the "6" count with a two input AND/NAND gate and reset the
counter. IIRC, the '93 contains a built in two input NAND gate in the
reset circuit, so these inputs needs only be connected to the two most
significant outputs of the divide by 8 counter. The required 100 kHz
output can be taken from the most significant output (it has a 66:33
output ratio). If you need 50:50 ratio, first divide by 8 in the first
'93, then by 6 in the second '93 and then by two in the independent
section in the first '93.

An alternate is to use a chain of presettable binary or decade
counters such as the 74HC160 or 74HC190 families. Or use
74F series to assure high speed...

Since you have a need to divide by 96, a 7-stage binary chain
that would normally divide by 128 can be preset to a state of 32
at the end of the count. The count chain then goes through 96
states before reaching the end of the count again...which can
initiate the preset. [all the other stages not preset would be
tied to ground] The 8th stage would simply be unused

Initiating the preset pulse can be a simple C-R coupling to get
about a 40 nanoSecond spike at the end of the count. If you
think you need it, you can use a spare inverter or a single bipolar
to couple the end-of-count transition spike into the Load pins.

With the 190 family you get a choice of Up or Down counting to
ease your arithmetic...which can be adapted to the division
control lines if there are a lot of different states selected.

I'd recommend synchronous counter ICs running at 9.6 MHz.

With the 190 series the input loading is only two gate inputs for
parallel synchronism using two binary ICs. Same with the
Parallel Load line. Internal chip buffering handles those. Only
two 16-pin DIPs needed to do the job. Some of the older
datasheets have example circuitry for preset counting. The 160
and 190 families have been around for a few decades, are still
used in new designs and still available.

Len Anderson
retired (from regular hours) electronic engineer person