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On Thu, 18 Mar 2004 10:42:22 +1000, Tony wrote:
Ignoring most of the previous posts in this thread (sorry - I deleted them) it occurs to me that maybe the problem may be the relatively low impedance load on the buffer, whose finite output impedance therefore causes some waveform distortion and loss of 5th harmonic. So how about a hi-Z parallel tank coupling circuit; for 17.2MHz (say 4p7 || 18uH) into a load of 100-500 ohms (say a 1k pot + 100n to Gnd, to see the effect of load variations), then into another 74AC buffer? Tony (remove the "_" to reply by email) Actually the tank's output will be biased to half-rail, which won't necessarily bias the CMOS output buffer properly. May need to cap-couple to the buffer, with a feedback resistor so it will self-bias (another case of reading the post AFTER hitting "send"). Tony (remove the "_" to reply by email) |
On Wed, 17 Mar 2004 23:43:57 +0000, Paul Burridge
wrote: On 17 Mar 2004 12:31:14 -0800, (Tom Bruhns) wrote: Paul Burridge wrote in message . .. ... What leads you to believe I have enough 5th harmonic in *my* particular case? The trace on the web site you provided a link to. The fact that you're using HC logic (which has inherent rise and fall times rather faster than the square wave source I used in my experiment). Your avering that the duty cycle is very nearly 50%. That's not to say you aren't doing something to kill it, but it's NOT difficult to extract it. Note that the subject you put on this thread really nails it: all you need to do is extract (and possibly amplify, depending on the final power level you need) what's already there. Now go do it. But feeding the whole square wave to the amplifier stage is a BAD idea because you can inadventently change the duty cycle (as seen at that amplifier's output) to one where the fifth is nulled. If you only need a few milliwatts, you can get that from the square wave directly, if the source impedance is low enough, simply by using the proper filter. Yes, but I'd hoped to avoid any intermediate amplification stages. Looks like I'll have to swallow it. --- That doesn't make any sense from the point of view that you've already posted a schematic showing a couple of gain stages. How much 17 MHz. do you really need and what does what you want to feed it into look like? |
Paul Burridge wrote in message . ..
Yes, but I'd hoped to avoid any intermediate amplification stages. Looks like I'll have to swallow it. Exactly how much power do you need? Exactly how "clean" (free from other harmonics) must it be? Don't you have an amplifier in the circuit you're playing with anyway? 100mW should be easy with a single stage following the digital square wave, and a full watt is certainly feasible with the right design. If you were hoping for 100mW of fifth harmonic from a single HC output, you were probably dreaming. |
Paul Burridge wrote in message . ..
Yes, but I'd hoped to avoid any intermediate amplification stages. Looks like I'll have to swallow it. Exactly how much power do you need? Exactly how "clean" (free from other harmonics) must it be? Don't you have an amplifier in the circuit you're playing with anyway? 100mW should be easy with a single stage following the digital square wave, and a full watt is certainly feasible with the right design. If you were hoping for 100mW of fifth harmonic from a single HC output, you were probably dreaming. |
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On Thu, 18 Mar 2004 11:33:17 +1000, Tony wrote:
On Thu, 18 Mar 2004 10:42:22 +1000, Tony wrote: Ignoring most of the previous posts in this thread (sorry - I deleted them) it occurs to me that maybe the problem may be the relatively low impedance load on the buffer, whose finite output impedance therefore causes some waveform distortion and loss of 5th harmonic. So how about a hi-Z parallel tank coupling circuit; for 17.2MHz (say 4p7 || 18uH) into a load of 100-500 ohms (say a 1k pot + 100n to Gnd, to see the effect of load variations), then into another 74AC buffer? Tony (remove the "_" to reply by email) Actually the tank's output will be biased to half-rail, which won't necessarily bias the CMOS output buffer properly. May need to cap-couple to the buffer, with a feedback resistor so it will self-bias (another case of reading the post AFTER hitting "send"). There's a lot of that goes on here. :-) I'll look into the idea, thanks. -- The BBC: Licensed at public expense to spread lies. |
On Thu, 18 Mar 2004 11:33:17 +1000, Tony wrote:
On Thu, 18 Mar 2004 10:42:22 +1000, Tony wrote: Ignoring most of the previous posts in this thread (sorry - I deleted them) it occurs to me that maybe the problem may be the relatively low impedance load on the buffer, whose finite output impedance therefore causes some waveform distortion and loss of 5th harmonic. So how about a hi-Z parallel tank coupling circuit; for 17.2MHz (say 4p7 || 18uH) into a load of 100-500 ohms (say a 1k pot + 100n to Gnd, to see the effect of load variations), then into another 74AC buffer? Tony (remove the "_" to reply by email) Actually the tank's output will be biased to half-rail, which won't necessarily bias the CMOS output buffer properly. May need to cap-couple to the buffer, with a feedback resistor so it will self-bias (another case of reading the post AFTER hitting "send"). There's a lot of that goes on here. :-) I'll look into the idea, thanks. -- The BBC: Licensed at public expense to spread lies. |
Paul Burridge wrote in message . ..
Exactly how much power do you need? Only enough to feed another inverter gate. Egad, Paul! You've been wasting this much net bandwidth just to drive another HC gate?? All you need is a filter/matching circuit that steps up the voltage. This is DOG SIMPLE! See below. Exactly how "clean" (free from other harmonics) must it be? Preferably filthy. It's another multiplier (this time only 3X, thank God!) Then you need a clean enough input that you'll get the desired output purity. "Filthy" is likely NOT the right answer and will just get you into further trouble. But fortunately, "clean" is simple, and "really clean" isn't at all difficult. Try this: square wave output -- I don't recall your exact freq; I used 3.7MHz -- from HC gate, feeds 4.58pF capacitor (make at least that one tuneable). Other end of cap feeds 20uH inductor, Qu=200. Other end of that inductor connects to next gate input, and net 18.6pF of capacitance to ground: say 15pF cap plus 3.6pF of gate input capacitance. For DC bias, gate input to ground = 22kohms; gate input to Vcc = 47kohms. That keeps the gate in a valid logic state when there's no excitation. Assuming the gate's RF input resistance at 18MHz is at least 2.5kohms, you should get a voltage gain at the fifth harmonic of about 15dB, which will be ample to drive the gate input. The available current from the filter is low enough that the gate's input protection diodes should clamp things nicely at the rails. Be sure to use a gate that has input protection, or else add low-capacitance, fast diodes externally. Gain at the third and seventh is down 20dB or so from that. If it needs to be cleaner than that, you can add a second resonator. The gate biasing suggested may result in an output duty cycle significantly different from 50%. If you will always have 3.7MHz drive, you can bias the input more in the center of its range, or even rearrange the circuit a bit and use a feedback resistor from output to input to set the DC bias. The gate's input impedance is then much lower, but you don't need much voltage to drive it. Don't use that trick with a Schmitt trigger input, though. 69 turns of 36AWG (0.125mm) wire, spaced 2 wire diameters c-c, on an 0.375" former, should give you about 20uH at Qu=200 and first parallel SRF about 50MHz, but you should be able to make it more compact using something like a T-50-2 powdered iron core. |
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