I read in sci.electronics.design that Rene Tschaggelar
wrote (in ) about 'Shielding
data lines to RF circuits', on Thu, 1 Apr 2004:
John Woodgate wrote:
I read in sci.electronics.design that Rene Tschaggelar
wrote (in ) about 'Shielding
data lines to RF circuits', on Thu, 1 Apr 2004:

What attenuator are you using ?
-100dBm is a lot of attenuation.


No, it's only 1 dB of attenuation from -99 dBm. 100 dB is a lot of
attenuation (or gain).

Got me John,
So how to get -99dBm, considering the DDS outputs in the
order of 0dBm.
Are there any decent digital step attenuators around ?
The better switches available at minicircuits have an isolation
of 80dB when off, their analog Attenuator has a range of 55dB.
In 2 stages then ?

Yes, it's often the simplest solution.
--
Regards, John Woodgate, OOO - Own Opinions Only.
The good news is that nothing is compulsory.
The bad news is that everything is prohibited.
http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk

I thought I would use switched sections with various sections switched
by relays - each section shielded if necessary.
The DDS will give an output down to -50dBm or so under software control,
though spurious outputs are not necessarily attenuated by the same
amount, so it is probably not a good idea to use the full attenuation range
My board will be double sided unless I *need* to use a more expensive board

Richard

Rene Tschaggelar wrote:
What attenuator are you using ?
-100dBm is a lot of attenuation.

Rene

Richard Hosking wrote:

Many thanks for the replies
That has given me some ideas for a start

Richard


Richard Hosking wrote:

Dear all
I want to design a DDS board which has attenuators on the output to
provide a low level output (-100dBm)
I have a venerable HP8640B which can give a calibrated output to -137dBm
To achieve this HP have gone to extraordinary lengths to shield the
oscillator attenuator/output amp circuits and any control lines - I
note there are at least two stages of bypassing/low pass filtering
with an intermediate shielded section

My question is: how do I get data and power lines into my DDS chip
(in a shielded enclosure) and prevent RF leakage out which will limit
the useful minimum level out from the DDS board?
I presume I will have to use a buffer of some sort for the data lines
and extensive bypassing on the power lines. I want reasoanbly quick
update speeds for my DDS, which is a serial port, which will mean
data rates in the MHz region.

I thought I would use switched sections with various sections switched
by relays - each section shielded if necessary.
The DDS will give an output down to -50dBm or so under software control,
though spurious outputs are not necessarily attenuated by the same
amount, so it is probably not a good idea to use the full attenuation range
My board will be double sided unless I *need* to use a more expensive board

Richard

Rene Tschaggelar wrote:
What attenuator are you using ?
-100dBm is a lot of attenuation.

Rene

Richard Hosking wrote:

Many thanks for the replies
That has given me some ideas for a start

Richard


Richard Hosking wrote:

Dear all
I want to design a DDS board which has attenuators on the output to
provide a low level output (-100dBm)
I have a venerable HP8640B which can give a calibrated output to -137dBm
To achieve this HP have gone to extraordinary lengths to shield the
oscillator attenuator/output amp circuits and any control lines - I
note there are at least two stages of bypassing/low pass filtering
with an intermediate shielded section

My question is: how do I get data and power lines into my DDS chip
(in a shielded enclosure) and prevent RF leakage out which will limit
the useful minimum level out from the DDS board?
I presume I will have to use a buffer of some sort for the data lines
and extensive bypassing on the power lines. I want reasoanbly quick
update speeds for my DDS, which is a serial port, which will mean
data rates in the MHz region.

I'm on a similar project and had a look at these issues.
Depending on the frequency and the relay, the isolation of an
off contact can be as low as 25dB. I assume you'd plan on changers
(SPDT) with the idle on 50 Ohms. The relay attenuator sure uses
a lot of board state.
The minicircuits variable attenuator unfortunately doesn't go to DC,
and while spec'ed to 10MHz, I didn't measure the lower border myself
yet. The minicircuits step attenuator have no steps greater than 20dB
and are rather pricey. They also have a lower border of 10MHz.

I'm also not yet sure how to get rid of the digital noise, especially
when using high update rates. I'm considering an FPGA to have the
lowest possible digital clock frequency for the amount of operations.

Rene



Richard Hosking wrote:
I thought I would use switched sections with various sections switched
by relays - each section shielded if necessary.
The DDS will give an output down to -50dBm or so under software control,
though spurious outputs are not necessarily attenuated by the same
amount, so it is probably not a good idea to use the full attenuation range
My board will be double sided unless I *need* to use a more expensive board

Richard

Rene Tschaggelar wrote:

What attenuator are you using ?
-100dBm is a lot of attenuation.

Rene

Richard Hosking wrote:

Many thanks for the replies
That has given me some ideas for a start

Richard


Richard Hosking wrote:

Dear all
I want to design a DDS board which has attenuators on the output to
provide a low level output (-100dBm)
I have a venerable HP8640B which can give a calibrated output to
-137dBm
To achieve this HP have gone to extraordinary lengths to shield the
oscillator attenuator/output amp circuits and any control lines - I
note there are at least two stages of bypassing/low pass filtering
with an intermediate shielded section

My question is: how do I get data and power lines into my DDS chip
(in a shielded enclosure) and prevent RF leakage out which will
limit the useful minimum level out from the DDS board?
I presume I will have to use a buffer of some sort for the data
lines and extensive bypassing on the power lines. I want reasoanbly
quick update speeds for my DDS, which is a serial port, which will
mean data rates in the MHz region.

I'm on a similar project and had a look at these issues.
Depending on the frequency and the relay, the isolation of an
off contact can be as low as 25dB. I assume you'd plan on changers
(SPDT) with the idle on 50 Ohms. The relay attenuator sure uses
a lot of board state.
The minicircuits variable attenuator unfortunately doesn't go to DC,
and while spec'ed to 10MHz, I didn't measure the lower border myself
yet. The minicircuits step attenuator have no steps greater than 20dB
and are rather pricey. They also have a lower border of 10MHz.

I'm also not yet sure how to get rid of the digital noise, especially
when using high update rates. I'm considering an FPGA to have the
lowest possible digital clock frequency for the amount of operations.

Rene



Richard Hosking wrote:
I thought I would use switched sections with various sections switched
by relays - each section shielded if necessary.
The DDS will give an output down to -50dBm or so under software control,
though spurious outputs are not necessarily attenuated by the same
amount, so it is probably not a good idea to use the full attenuation range
My board will be double sided unless I *need* to use a more expensive board

Richard

Rene Tschaggelar wrote:

What attenuator are you using ?
-100dBm is a lot of attenuation.

Rene

Richard Hosking wrote:

Many thanks for the replies
That has given me some ideas for a start

Richard


Richard Hosking wrote:

Dear all
I want to design a DDS board which has attenuators on the output to
provide a low level output (-100dBm)
I have a venerable HP8640B which can give a calibrated output to
-137dBm
To achieve this HP have gone to extraordinary lengths to shield the
oscillator attenuator/output amp circuits and any control lines - I
note there are at least two stages of bypassing/low pass filtering
with an intermediate shielded section

My question is: how do I get data and power lines into my DDS chip
(in a shielded enclosure) and prevent RF leakage out which will
limit the useful minimum level out from the DDS board?
I presume I will have to use a buffer of some sort for the data
lines and extensive bypassing on the power lines. I want reasoanbly
quick update speeds for my DDS, which is a serial port, which will
mean data rates in the MHz region.