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Phase frequency Detector
Hi!
I need help understanding a conventional phase/frequency detector.I consists of 6 two input NAND gates and 3 three input NAND gates.It compares the phase and generates UP and DOWN signals.I was wondering why the dead zone is high specially when there is a large reset delay path. Deepthi |
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There are various fixes for the dead zone problem.
In the mid-1970's, Fairchild (the original company) sold an "11C44" phase detector that got rid of the dead zone by injecting a narrow pulse so that the phase detector pulses would never have to try to go to zero width. Eric Breeze holds the patent on this technique; if interested read his patent. Analog Devices makes that AD9901 phase detector which gets around the dead zone by first dividing the frequency by 2. However, it is not suitable for a frequency synthesizer because of the large spurious sidebands resulting from this technique. Motorola had some patents on the circuits in its MC145159 that dealt with the dead zone and sampling sidebands. It also used a divide by 2 technique, that was not documented; (we figured it out by observing the chip's output). That chip may have been inherited by On Semiconductor. It was originally developed for some division of GE. Rick N6RK "Avery Fineman" wrote in message ... In article , (Deepthi) writes: Hi! I need help understanding a conventional phase/frequency detector.I consists of 6 two input NAND gates and 3 three input NAND gates.It compares the phase and generates UP and DOWN signals.I was wondering why the dead zone is high specially when there is a large reset delay path. Deepthi The "conventional phase-frequency detector" I know is the basic circuit of the Motorola MC4044 package. That one is explained in detail - in the form of a timing chart of ALL gate states with little arrows indicating which gate acts on other gates - in the September, 1982, issue of HAM RADIO Magazine in the "Digital Techniques" column titled "Inside A Phase-Frequency Detector (MC4044)." The particular timing diagram is rather straightforward waveform diagrams rather than the symbolic logic-state graphics others have used. I am the author of that column. The "dead zone" you mention is due to differential gate delays and can be minimized with high-speed logic families. It has several causes depending on whether the signal input is leading or lagging the reference input. The waveform diagram lets you select either one and, with a schematic, see the path that causes the differential gate delay. Len Anderson retired (from regular hours) electronic engineer person |
In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK"
writes: There are various fixes for the dead zone problem. In the mid-1970's, Fairchild (the original company) sold an "11C44" phase detector that got rid of the dead zone by injecting a narrow pulse so that the phase detector pulses would never have to try to go to zero width. Eric Breeze holds the patent on this technique; if interested read his patent. Analog Devices makes that AD9901 phase detector which gets around the dead zone by first dividing the frequency by 2. However, it is not suitable for a frequency synthesizer because of the large spurious sidebands resulting from this technique. Motorola had some patents on the circuits in its MC145159 that dealt with the dead zone and sampling sidebands. It also used a divide by 2 technique, that was not documented; (we figured it out by observing the chip's output). That chip may have been inherited by On Semiconductor. It was originally developed for some division of GE. The "dead zone problem" is less a problem and more a state of mind. :-) When implemented with a charge-pump circuit (voltage & time converter to current) between the PFD and loop filter, it rather disappears into the woodwork of the whole PLL. The phase difference between signal and reference is proportional to the control voltage of the VCO producing the basic frequency. There is ALWAYS going to be a signal versus reference phase offset when the entire loop is in lock so this dreaded "dead zone problem" will only show up in a very narrow range of controlled frequency. General intuitive thought on any PLL or other synthesizer closed loop is that the relative phase between signal and reference is zero. It isn't. If it was, then the VCO could not be controlled. As a very rough indicator of VCO frequency, that signal v. reference offset phase exists for quick scope checking...when the control voltage range of the VCO is known. Good for a quick bench check. In practical terms, that dreaded "dead zone" isn't visible in a real-world example. Case in point: 23+ years ago, Rocketdyne Division of Rockwell International (now a Division of Boeing) was beginning work on a Deformable Mirror for laser work (they had a sizeable optics group) that used a 1 MHz signal out of optics to indicate the light phase error of an optical interferometer. I rigged up a 74H family phase-frequency detector circuit as the heart of that, an integrator out of that into an A-to-D converter to get a digital version for computer data manipulation. By all the careful measurement, the expected dead zone didn't show up on any graphing and the standard lab time interval counters could resolve, accurately, 2 nanoseconds using time averaging. [translates to rather less than a degree of phase error] The optical physicists had been hopping up and down about "dead zone" in meetings but the actual circuit performance didn't show it. One reason for the non-observation of any dead zone is that the digital gates forming the PFD were so lightly loaded in other-gate capacitance that their propagation delays all tended to be the same. Datasheet values of propagation delay of gates are all given as maximums, rather worst-case things with lots of pFds connected to outputs, etc. Put on half a prototype board, loaded only by other gates of the PFD and the resistor input of an op-amp integrator, the capacitance loading was minimal. [project was successful, and spawned more work on deformable mirrors] It can be an interesting academic problem to achieve a zero dead- dead zone effect in a PFD, but thats about it. When working at the comparison frequency of less than a few MHz, the PFD dead zone due to differential propagation delays of the gates disappears into the woodwork when using 74LS or faster digital families. There's plenty to be concerned about in any frequency synthesizer subsystem, but a phase-frequency detector gate structure is a very minor problem in my opinion. DDS and fractional-N loops in synthesizers have their own problems such as spurious output, but those problems can't really be traced to any PFD dead-zone effect. A PFD is wonderful as a control loop element in that it can control a VCO (of the loop) from way off the frequency and bring it into a lock phase range...from either worst- case start-up frequency. [way back in the beginning of radio time, lock loops had to use sawtooth sweep circuits to cure that start-up condition, and couldn't control beyond +/- 90 degrees of phase shift...PFDs easily handle +/-180 degrees] Len Anderson retired (from regular hours) electronic engineer person |
In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK"
writes: There are various fixes for the dead zone problem. In the mid-1970's, Fairchild (the original company) sold an "11C44" phase detector that got rid of the dead zone by injecting a narrow pulse so that the phase detector pulses would never have to try to go to zero width. Eric Breeze holds the patent on this technique; if interested read his patent. Analog Devices makes that AD9901 phase detector which gets around the dead zone by first dividing the frequency by 2. However, it is not suitable for a frequency synthesizer because of the large spurious sidebands resulting from this technique. Motorola had some patents on the circuits in its MC145159 that dealt with the dead zone and sampling sidebands. It also used a divide by 2 technique, that was not documented; (we figured it out by observing the chip's output). That chip may have been inherited by On Semiconductor. It was originally developed for some division of GE. The "dead zone problem" is less a problem and more a state of mind. :-) When implemented with a charge-pump circuit (voltage & time converter to current) between the PFD and loop filter, it rather disappears into the woodwork of the whole PLL. The phase difference between signal and reference is proportional to the control voltage of the VCO producing the basic frequency. There is ALWAYS going to be a signal versus reference phase offset when the entire loop is in lock so this dreaded "dead zone problem" will only show up in a very narrow range of controlled frequency. General intuitive thought on any PLL or other synthesizer closed loop is that the relative phase between signal and reference is zero. It isn't. If it was, then the VCO could not be controlled. As a very rough indicator of VCO frequency, that signal v. reference offset phase exists for quick scope checking...when the control voltage range of the VCO is known. Good for a quick bench check. In practical terms, that dreaded "dead zone" isn't visible in a real-world example. Case in point: 23+ years ago, Rocketdyne Division of Rockwell International (now a Division of Boeing) was beginning work on a Deformable Mirror for laser work (they had a sizeable optics group) that used a 1 MHz signal out of optics to indicate the light phase error of an optical interferometer. I rigged up a 74H family phase-frequency detector circuit as the heart of that, an integrator out of that into an A-to-D converter to get a digital version for computer data manipulation. By all the careful measurement, the expected dead zone didn't show up on any graphing and the standard lab time interval counters could resolve, accurately, 2 nanoseconds using time averaging. [translates to rather less than a degree of phase error] The optical physicists had been hopping up and down about "dead zone" in meetings but the actual circuit performance didn't show it. One reason for the non-observation of any dead zone is that the digital gates forming the PFD were so lightly loaded in other-gate capacitance that their propagation delays all tended to be the same. Datasheet values of propagation delay of gates are all given as maximums, rather worst-case things with lots of pFds connected to outputs, etc. Put on half a prototype board, loaded only by other gates of the PFD and the resistor input of an op-amp integrator, the capacitance loading was minimal. [project was successful, and spawned more work on deformable mirrors] It can be an interesting academic problem to achieve a zero dead- dead zone effect in a PFD, but thats about it. When working at the comparison frequency of less than a few MHz, the PFD dead zone due to differential propagation delays of the gates disappears into the woodwork when using 74LS or faster digital families. There's plenty to be concerned about in any frequency synthesizer subsystem, but a phase-frequency detector gate structure is a very minor problem in my opinion. DDS and fractional-N loops in synthesizers have their own problems such as spurious output, but those problems can't really be traced to any PFD dead-zone effect. A PFD is wonderful as a control loop element in that it can control a VCO (of the loop) from way off the frequency and bring it into a lock phase range...from either worst- case start-up frequency. [way back in the beginning of radio time, lock loops had to use sawtooth sweep circuits to cure that start-up condition, and couldn't control beyond +/- 90 degrees of phase shift...PFDs easily handle +/-180 degrees] Len Anderson retired (from regular hours) electronic engineer person |
"Avery Fineman" wrote in message
... In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK" writes: There are various fixes for the dead zone problem. In the mid-1970's, Fairchild (the original company) sold an "11C44" phase detector that got rid of the dead zone by injecting a narrow pulse so that the phase detector pulses would never have to try to go to zero width. Eric Breeze holds the patent on this technique; if interested read his patent. Analog Devices makes that AD9901 phase detector which gets around the dead zone by first dividing the frequency by 2. However, it is not suitable for a frequency synthesizer because of the large spurious sidebands resulting from this technique. Motorola had some patents on the circuits in its MC145159 that dealt with the dead zone and sampling sidebands. It also used a divide by 2 technique, that was not documented; (we figured it out by observing the chip's output). That chip may have been inherited by On Semiconductor. It was originally developed for some division of GE. The "dead zone problem" is less a problem and more a state of mind. :-) When implemented with a charge-pump circuit (voltage & time converter to current) between the PFD and loop filter, it rather disappears into the woodwork of the whole PLL. The phase difference between signal and reference is proportional to the control voltage of the VCO producing the basic frequency. There is ALWAYS going to be a signal versus reference phase offset when the entire loop is in lock so this dreaded "dead zone problem" will only show up in a very narrow range of controlled frequency. General intuitive thought on any PLL or other synthesizer closed loop is that the relative phase between signal and reference is zero. It isn't. If it was, then the VCO could not be controlled. As a very rough indicator of VCO frequency, that signal v. reference offset phase exists for quick scope checking...when the control voltage range of the VCO is known. Good for a quick bench check. In practical terms, that dreaded "dead zone" isn't visible in a real-world example. Case in point: 23+ years ago, Rocketdyne Division of Rockwell International (now a Division of Boeing) was beginning work on a Deformable Mirror for laser work (they had a sizeable optics group) that used a 1 MHz signal out of optics to indicate the light phase error of an optical interferometer. I rigged up a 74H family phase-frequency detector circuit as the heart of that, an integrator out of that into an A-to-D converter to get a digital version for computer data manipulation. By all the careful measurement, the expected dead zone didn't show up on any graphing and the standard lab time interval counters could resolve, accurately, 2 nanoseconds using time averaging. [translates to rather less than a degree of phase error] The optical physicists had been hopping up and down about "dead zone" in meetings but the actual circuit performance didn't show it. One reason for the non-observation of any dead zone is that the digital gates forming the PFD were so lightly loaded in other-gate capacitance that their propagation delays all tended to be the same. Datasheet values of propagation delay of gates are all given as maximums, rather worst-case things with lots of pFds connected to outputs, etc. Put on half a prototype board, loaded only by other gates of the PFD and the resistor input of an op-amp integrator, the capacitance loading was minimal. [project was successful, and spawned more work on deformable mirrors] It can be an interesting academic problem to achieve a zero dead- dead zone effect in a PFD, but thats about it. When working at the comparison frequency of less than a few MHz, the PFD dead zone due to differential propagation delays of the gates disappears into the woodwork when using 74LS or faster digital families. There's plenty to be concerned about in any frequency synthesizer subsystem, but a phase-frequency detector gate structure is a very minor problem in my opinion. DDS and fractional-N loops in synthesizers have their own problems such as spurious output, but those problems can't really be traced to any PFD dead-zone effect. A PFD is wonderful as a control loop element in that it can control a VCO (of the loop) from way off the frequency and bring it into a lock phase range...from either worst- case start-up frequency. [way back in the beginning of radio time, lock loops had to use sawtooth sweep circuits to cure that start-up condition, and couldn't control beyond +/- 90 degrees of phase shift...PFDs easily handle +/-180 degrees] Len Anderson retired (from regular hours) electronic engineer person Len - Avery, whomever, Our experiences differ. When designing PLL synths back then for two-war radio, we always saw the dead zone. In a type 2 loop (hope I'm remembering my control theory correctly) the extra integration allows the VCO to float around within the dead zone, causing a low freq rumble at times. You could watch the phase wandering around on a scope on the two PD inputs. We would force some small leakage current just to hold it up against one side of the dead zone. Perhaps the types of requirements causes the difference. We were in the audio range with the PD reference freq and lock times in the tens of ms. if I recall correctly. If I recall, the Fairchild chip did a better job of matching the delays. The small overlap causing a narrow pulse to occur seemed like a small issue - not much energy at the ref freq for some applications. Our synthesizers were of such requirements that there was a very tight balance between lock time and spurious. The loop filtering took much care to get the lock time and keep reference spurs down. I designed and built what I still believe is the first 2-meter synth hand held in 1973. 8.0 ma current max drain (varied 'tween 6.5 and 8 across the band), 70dB spurious (the radio originally was 43 dB). 5kc resolution. In a Motorola HT-220. Still have it. A year later I got tired of doing the dip-switches and designed a keyboard entry system. That fella with the HT-220 site didn't put it on. He does have Dale Heatherington's (sp) though (got a couple of them also). -- Steve N, K,9;d, c. i My email has no u's. |
"Avery Fineman" wrote in message
... In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK" writes: There are various fixes for the dead zone problem. In the mid-1970's, Fairchild (the original company) sold an "11C44" phase detector that got rid of the dead zone by injecting a narrow pulse so that the phase detector pulses would never have to try to go to zero width. Eric Breeze holds the patent on this technique; if interested read his patent. Analog Devices makes that AD9901 phase detector which gets around the dead zone by first dividing the frequency by 2. However, it is not suitable for a frequency synthesizer because of the large spurious sidebands resulting from this technique. Motorola had some patents on the circuits in its MC145159 that dealt with the dead zone and sampling sidebands. It also used a divide by 2 technique, that was not documented; (we figured it out by observing the chip's output). That chip may have been inherited by On Semiconductor. It was originally developed for some division of GE. The "dead zone problem" is less a problem and more a state of mind. :-) When implemented with a charge-pump circuit (voltage & time converter to current) between the PFD and loop filter, it rather disappears into the woodwork of the whole PLL. The phase difference between signal and reference is proportional to the control voltage of the VCO producing the basic frequency. There is ALWAYS going to be a signal versus reference phase offset when the entire loop is in lock so this dreaded "dead zone problem" will only show up in a very narrow range of controlled frequency. General intuitive thought on any PLL or other synthesizer closed loop is that the relative phase between signal and reference is zero. It isn't. If it was, then the VCO could not be controlled. As a very rough indicator of VCO frequency, that signal v. reference offset phase exists for quick scope checking...when the control voltage range of the VCO is known. Good for a quick bench check. In practical terms, that dreaded "dead zone" isn't visible in a real-world example. Case in point: 23+ years ago, Rocketdyne Division of Rockwell International (now a Division of Boeing) was beginning work on a Deformable Mirror for laser work (they had a sizeable optics group) that used a 1 MHz signal out of optics to indicate the light phase error of an optical interferometer. I rigged up a 74H family phase-frequency detector circuit as the heart of that, an integrator out of that into an A-to-D converter to get a digital version for computer data manipulation. By all the careful measurement, the expected dead zone didn't show up on any graphing and the standard lab time interval counters could resolve, accurately, 2 nanoseconds using time averaging. [translates to rather less than a degree of phase error] The optical physicists had been hopping up and down about "dead zone" in meetings but the actual circuit performance didn't show it. One reason for the non-observation of any dead zone is that the digital gates forming the PFD were so lightly loaded in other-gate capacitance that their propagation delays all tended to be the same. Datasheet values of propagation delay of gates are all given as maximums, rather worst-case things with lots of pFds connected to outputs, etc. Put on half a prototype board, loaded only by other gates of the PFD and the resistor input of an op-amp integrator, the capacitance loading was minimal. [project was successful, and spawned more work on deformable mirrors] It can be an interesting academic problem to achieve a zero dead- dead zone effect in a PFD, but thats about it. When working at the comparison frequency of less than a few MHz, the PFD dead zone due to differential propagation delays of the gates disappears into the woodwork when using 74LS or faster digital families. There's plenty to be concerned about in any frequency synthesizer subsystem, but a phase-frequency detector gate structure is a very minor problem in my opinion. DDS and fractional-N loops in synthesizers have their own problems such as spurious output, but those problems can't really be traced to any PFD dead-zone effect. A PFD is wonderful as a control loop element in that it can control a VCO (of the loop) from way off the frequency and bring it into a lock phase range...from either worst- case start-up frequency. [way back in the beginning of radio time, lock loops had to use sawtooth sweep circuits to cure that start-up condition, and couldn't control beyond +/- 90 degrees of phase shift...PFDs easily handle +/-180 degrees] Len Anderson retired (from regular hours) electronic engineer person Len - Avery, whomever, Our experiences differ. When designing PLL synths back then for two-war radio, we always saw the dead zone. In a type 2 loop (hope I'm remembering my control theory correctly) the extra integration allows the VCO to float around within the dead zone, causing a low freq rumble at times. You could watch the phase wandering around on a scope on the two PD inputs. We would force some small leakage current just to hold it up against one side of the dead zone. Perhaps the types of requirements causes the difference. We were in the audio range with the PD reference freq and lock times in the tens of ms. if I recall correctly. If I recall, the Fairchild chip did a better job of matching the delays. The small overlap causing a narrow pulse to occur seemed like a small issue - not much energy at the ref freq for some applications. Our synthesizers were of such requirements that there was a very tight balance between lock time and spurious. The loop filtering took much care to get the lock time and keep reference spurs down. I designed and built what I still believe is the first 2-meter synth hand held in 1973. 8.0 ma current max drain (varied 'tween 6.5 and 8 across the band), 70dB spurious (the radio originally was 43 dB). 5kc resolution. In a Motorola HT-220. Still have it. A year later I got tired of doing the dip-switches and designed a keyboard entry system. That fella with the HT-220 site didn't put it on. He does have Dale Heatherington's (sp) though (got a couple of them also). -- Steve N, K,9;d, c. i My email has no u's. |
Dead-zone = phase noise. Very little dead-zone = very little phase noise.
Bigger dead-zone = bigger phase noise. You can interpolate the rest for yourself. Joe W3JDR "Avery Fineman" wrote in message ... In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK" writes: There are various fixes for the dead zone problem. In the mid-1970's, Fairchild (the original company) sold an "11C44" phase detector that got rid of the dead zone by injecting a narrow pulse so that the phase detector pulses would never have to try to go to zero width. Eric Breeze holds the patent on this technique; if interested read his patent. Analog Devices makes that AD9901 phase detector which gets around the dead zone by first dividing the frequency by 2. However, it is not suitable for a frequency synthesizer because of the large spurious sidebands resulting from this technique. Motorola had some patents on the circuits in its MC145159 that dealt with the dead zone and sampling sidebands. It also used a divide by 2 technique, that was not documented; (we figured it out by observing the chip's output). That chip may have been inherited by On Semiconductor. It was originally developed for some division of GE. The "dead zone problem" is less a problem and more a state of mind. :-) When implemented with a charge-pump circuit (voltage & time converter to current) between the PFD and loop filter, it rather disappears into the woodwork of the whole PLL. The phase difference between signal and reference is proportional to the control voltage of the VCO producing the basic frequency. There is ALWAYS going to be a signal versus reference phase offset when the entire loop is in lock so this dreaded "dead zone problem" will only show up in a very narrow range of controlled frequency. General intuitive thought on any PLL or other synthesizer closed loop is that the relative phase between signal and reference is zero. It isn't. If it was, then the VCO could not be controlled. As a very rough indicator of VCO frequency, that signal v. reference offset phase exists for quick scope checking...when the control voltage range of the VCO is known. Good for a quick bench check. In practical terms, that dreaded "dead zone" isn't visible in a real-world example. Case in point: 23+ years ago, Rocketdyne Division of Rockwell International (now a Division of Boeing) was beginning work on a Deformable Mirror for laser work (they had a sizeable optics group) that used a 1 MHz signal out of optics to indicate the light phase error of an optical interferometer. I rigged up a 74H family phase-frequency detector circuit as the heart of that, an integrator out of that into an A-to-D converter to get a digital version for computer data manipulation. By all the careful measurement, the expected dead zone didn't show up on any graphing and the standard lab time interval counters could resolve, accurately, 2 nanoseconds using time averaging. [translates to rather less than a degree of phase error] The optical physicists had been hopping up and down about "dead zone" in meetings but the actual circuit performance didn't show it. One reason for the non-observation of any dead zone is that the digital gates forming the PFD were so lightly loaded in other-gate capacitance that their propagation delays all tended to be the same. Datasheet values of propagation delay of gates are all given as maximums, rather worst-case things with lots of pFds connected to outputs, etc. Put on half a prototype board, loaded only by other gates of the PFD and the resistor input of an op-amp integrator, the capacitance loading was minimal. [project was successful, and spawned more work on deformable mirrors] It can be an interesting academic problem to achieve a zero dead- dead zone effect in a PFD, but thats about it. When working at the comparison frequency of less than a few MHz, the PFD dead zone due to differential propagation delays of the gates disappears into the woodwork when using 74LS or faster digital families. There's plenty to be concerned about in any frequency synthesizer subsystem, but a phase-frequency detector gate structure is a very minor problem in my opinion. DDS and fractional-N loops in synthesizers have their own problems such as spurious output, but those problems can't really be traced to any PFD dead-zone effect. A PFD is wonderful as a control loop element in that it can control a VCO (of the loop) from way off the frequency and bring it into a lock phase range...from either worst- case start-up frequency. [way back in the beginning of radio time, lock loops had to use sawtooth sweep circuits to cure that start-up condition, and couldn't control beyond +/- 90 degrees of phase shift...PFDs easily handle +/-180 degrees] Len Anderson retired (from regular hours) electronic engineer person |
Dead-zone = phase noise. Very little dead-zone = very little phase noise.
Bigger dead-zone = bigger phase noise. You can interpolate the rest for yourself. Joe W3JDR "Avery Fineman" wrote in message ... In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK" writes: There are various fixes for the dead zone problem. In the mid-1970's, Fairchild (the original company) sold an "11C44" phase detector that got rid of the dead zone by injecting a narrow pulse so that the phase detector pulses would never have to try to go to zero width. Eric Breeze holds the patent on this technique; if interested read his patent. Analog Devices makes that AD9901 phase detector which gets around the dead zone by first dividing the frequency by 2. However, it is not suitable for a frequency synthesizer because of the large spurious sidebands resulting from this technique. Motorola had some patents on the circuits in its MC145159 that dealt with the dead zone and sampling sidebands. It also used a divide by 2 technique, that was not documented; (we figured it out by observing the chip's output). That chip may have been inherited by On Semiconductor. It was originally developed for some division of GE. The "dead zone problem" is less a problem and more a state of mind. :-) When implemented with a charge-pump circuit (voltage & time converter to current) between the PFD and loop filter, it rather disappears into the woodwork of the whole PLL. The phase difference between signal and reference is proportional to the control voltage of the VCO producing the basic frequency. There is ALWAYS going to be a signal versus reference phase offset when the entire loop is in lock so this dreaded "dead zone problem" will only show up in a very narrow range of controlled frequency. General intuitive thought on any PLL or other synthesizer closed loop is that the relative phase between signal and reference is zero. It isn't. If it was, then the VCO could not be controlled. As a very rough indicator of VCO frequency, that signal v. reference offset phase exists for quick scope checking...when the control voltage range of the VCO is known. Good for a quick bench check. In practical terms, that dreaded "dead zone" isn't visible in a real-world example. Case in point: 23+ years ago, Rocketdyne Division of Rockwell International (now a Division of Boeing) was beginning work on a Deformable Mirror for laser work (they had a sizeable optics group) that used a 1 MHz signal out of optics to indicate the light phase error of an optical interferometer. I rigged up a 74H family phase-frequency detector circuit as the heart of that, an integrator out of that into an A-to-D converter to get a digital version for computer data manipulation. By all the careful measurement, the expected dead zone didn't show up on any graphing and the standard lab time interval counters could resolve, accurately, 2 nanoseconds using time averaging. [translates to rather less than a degree of phase error] The optical physicists had been hopping up and down about "dead zone" in meetings but the actual circuit performance didn't show it. One reason for the non-observation of any dead zone is that the digital gates forming the PFD were so lightly loaded in other-gate capacitance that their propagation delays all tended to be the same. Datasheet values of propagation delay of gates are all given as maximums, rather worst-case things with lots of pFds connected to outputs, etc. Put on half a prototype board, loaded only by other gates of the PFD and the resistor input of an op-amp integrator, the capacitance loading was minimal. [project was successful, and spawned more work on deformable mirrors] It can be an interesting academic problem to achieve a zero dead- dead zone effect in a PFD, but thats about it. When working at the comparison frequency of less than a few MHz, the PFD dead zone due to differential propagation delays of the gates disappears into the woodwork when using 74LS or faster digital families. There's plenty to be concerned about in any frequency synthesizer subsystem, but a phase-frequency detector gate structure is a very minor problem in my opinion. DDS and fractional-N loops in synthesizers have their own problems such as spurious output, but those problems can't really be traced to any PFD dead-zone effect. A PFD is wonderful as a control loop element in that it can control a VCO (of the loop) from way off the frequency and bring it into a lock phase range...from either worst- case start-up frequency. [way back in the beginning of radio time, lock loops had to use sawtooth sweep circuits to cure that start-up condition, and couldn't control beyond +/- 90 degrees of phase shift...PFDs easily handle +/-180 degrees] Len Anderson retired (from regular hours) electronic engineer person |
In article , "W3JDR"
writes: Dead-zone = phase noise. Very little dead-zone = very little phase noise. Bigger dead-zone = bigger phase noise. You can interpolate the rest for yourself. I have to disagree with some of that. First of all, a "dead zone" or the almost-exactly-in-phase condition, occurs at only one VCO frequency where the control voltage sets up the frequency for that in-phase condition. Yes, at that exact frequency, there COULD be some phase noise. But, the phase noise may NOT be from this "dead zone" effect. Phase noise can come from MANY different sources. If it occurs well away from the in-same-phase "dead zone" then the phase noise is NOT caused by any "dead zone." The relative phase between signal and reference inputs to a PFD correspond to the VCO control voltage (times the charge-pump or integrator circuit constants). Signal and reference phases when in lock will always be offset from one another, one leading and one lagging. A good loop will show a constant offset of phases even when both inputs hold a constant phase. Len Anderson |
In article , "W3JDR"
writes: Dead-zone = phase noise. Very little dead-zone = very little phase noise. Bigger dead-zone = bigger phase noise. You can interpolate the rest for yourself. I have to disagree with some of that. First of all, a "dead zone" or the almost-exactly-in-phase condition, occurs at only one VCO frequency where the control voltage sets up the frequency for that in-phase condition. Yes, at that exact frequency, there COULD be some phase noise. But, the phase noise may NOT be from this "dead zone" effect. Phase noise can come from MANY different sources. If it occurs well away from the in-same-phase "dead zone" then the phase noise is NOT caused by any "dead zone." The relative phase between signal and reference inputs to a PFD correspond to the VCO control voltage (times the charge-pump or integrator circuit constants). Signal and reference phases when in lock will always be offset from one another, one leading and one lagging. A good loop will show a constant offset of phases even when both inputs hold a constant phase. Len Anderson |
In article , "Steve Nosko"
writes: "Avery Fineman" wrote in message ... In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK" writes: There are various fixes for the dead zone problem. In the mid-1970's, Fairchild (the original company) sold an "11C44" phase detector that got rid of the dead zone by injecting a narrow pulse so that the phase detector pulses would never have to try to go to zero width. Eric Breeze holds the patent on this technique; if interested read his patent. Analog Devices makes that AD9901 phase detector which gets around the dead zone by first dividing the frequency by 2. However, it is not suitable for a frequency synthesizer because of the large spurious sidebands resulting from this technique. Motorola had some patents on the circuits in its MC145159 that dealt with the dead zone and sampling sidebands. It also used a divide by 2 technique, that was not documented; (we figured it out by observing the chip's output). That chip may have been inherited by On Semiconductor. It was originally developed for some division of GE. The "dead zone problem" is less a problem and more a state of mind. :-) When implemented with a charge-pump circuit (voltage & time converter to current) between the PFD and loop filter, it rather disappears into the woodwork of the whole PLL. The phase difference between signal and reference is proportional to the control voltage of the VCO producing the basic frequency. There is ALWAYS going to be a signal versus reference phase offset when the entire loop is in lock so this dreaded "dead zone problem" will only show up in a very narrow range of controlled frequency. General intuitive thought on any PLL or other synthesizer closed loop is that the relative phase between signal and reference is zero. It isn't. If it was, then the VCO could not be controlled. As a very rough indicator of VCO frequency, that signal v. reference offset phase exists for quick scope checking...when the control voltage range of the VCO is known. Good for a quick bench check. In practical terms, that dreaded "dead zone" isn't visible in a real-world example. Case in point: 23+ years ago, Rocketdyne Division of Rockwell International (now a Division of Boeing) was beginning work on a Deformable Mirror for laser work (they had a sizeable optics group) that used a 1 MHz signal out of optics to indicate the light phase error of an optical interferometer. I rigged up a 74H family phase-frequency detector circuit as the heart of that, an integrator out of that into an A-to-D converter to get a digital version for computer data manipulation. By all the careful measurement, the expected dead zone didn't show up on any graphing and the standard lab time interval counters could resolve, accurately, 2 nanoseconds using time averaging. [translates to rather less than a degree of phase error] The optical physicists had been hopping up and down about "dead zone" in meetings but the actual circuit performance didn't show it. One reason for the non-observation of any dead zone is that the digital gates forming the PFD were so lightly loaded in other-gate capacitance that their propagation delays all tended to be the same. Datasheet values of propagation delay of gates are all given as maximums, rather worst-case things with lots of pFds connected to outputs, etc. Put on half a prototype board, loaded only by other gates of the PFD and the resistor input of an op-amp integrator, the capacitance loading was minimal. [project was successful, and spawned more work on deformable mirrors] It can be an interesting academic problem to achieve a zero dead- dead zone effect in a PFD, but thats about it. When working at the comparison frequency of less than a few MHz, the PFD dead zone due to differential propagation delays of the gates disappears into the woodwork when using 74LS or faster digital families. There's plenty to be concerned about in any frequency synthesizer subsystem, but a phase-frequency detector gate structure is a very minor problem in my opinion. DDS and fractional-N loops in synthesizers have their own problems such as spurious output, but those problems can't really be traced to any PFD dead-zone effect. A PFD is wonderful as a control loop element in that it can control a VCO (of the loop) from way off the frequency and bring it into a lock phase range...from either worst- case start-up frequency. [way back in the beginning of radio time, lock loops had to use sawtooth sweep circuits to cure that start-up condition, and couldn't control beyond +/- 90 degrees of phase shift...PFDs easily handle +/-180 degrees] Len Anderson retired (from regular hours) electronic engineer person Len - Avery, whomever, Our experiences differ. When designing PLL synths back then for two-war radio, we always saw the dead zone. "Two-war radio?" PRC-25? Term not understood. Experience has hands-on with everything from a PRC-8 to a PRC-104, but little with the PRC-25 or -77. In a type 2 loop (hope I'm remembering my control theory correctly) the extra integration allows the VCO to float around within the dead zone, causing a low freq rumble at times. You could watch the phase wandering around on a scope on the two PD inputs. If the loop is set for something like a 10 to 50 mSec lock-in time, one has to look quick to see the actual lock-in. If the loop is designed properly (VCO control voltage gain, time relative to the reference frequency), there should not be any "wander." In order to see the settling time from a large step-function of frequency change, you need to sync a scope from the step source and watch the jump-and-settle of the control voltage like a damped sinewave. That's a quick check of loop control action. Storage scope (old way) or digital scope (muy better) are the best way to view that. We would force some small leakage current just to hold it up against one side of the dead zone. Perhaps the types of requirements causes the difference. We were in the audio range with the PD reference freq and lock times in the tens of ms. if I recall correctly. Most of the older PLLs had reference frequencies of 1 to 5 KHz. That's a period of 1.0 mS to 200 uS. Without about 5 to 10 cycles for settling-in (to near invisibility), that would be about 10 to 2 mS, rather quick. If I recall, the Fairchild chip did a better job of matching the delays. The small overlap causing a narrow pulse to occur seemed like a small issue - not much energy at the ref freq for some applications. Our synthesizers were of such requirements that there was a very tight balance between lock time and spurious. The loop filtering took much care to get the lock time and keep reference spurs down. Regardless of the loop filter type, those are always fussy to avoid pickup contamination of the VCO control line. But, knowing the control voltage characteristics (delta-V v. frequency) over a range, the design is strictly textbook formula stuff. It helps greatly if the VCO control characteristics are linear versus frequency AND the division ratio maximum to minimum number is as small as possible. I've seen a few applications where both the control voltage characteristics were very non-linear AND the division ratio of the PLL greater than 2:1 with the end result being an almost impossible lock at the extreme ends of the tuning range. One case was alleviated by extra circuitry from the division control to generate a DC bias summed with the control voltage. Not too swift since it took more parts, but better than failure. In my own case, the filtering and shielding around the PFD to VCO had to be rather severe in order to keep it stable (too much high-energy circuitry rather nearby). Once that was achieved, there was no wandering at a 1 KHz reference input with proper values of known control voltage constants and accurate calculation of loop filter values. It was "tight." Len Anderson |
In article , "Steve Nosko"
writes: "Avery Fineman" wrote in message ... In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK" writes: There are various fixes for the dead zone problem. In the mid-1970's, Fairchild (the original company) sold an "11C44" phase detector that got rid of the dead zone by injecting a narrow pulse so that the phase detector pulses would never have to try to go to zero width. Eric Breeze holds the patent on this technique; if interested read his patent. Analog Devices makes that AD9901 phase detector which gets around the dead zone by first dividing the frequency by 2. However, it is not suitable for a frequency synthesizer because of the large spurious sidebands resulting from this technique. Motorola had some patents on the circuits in its MC145159 that dealt with the dead zone and sampling sidebands. It also used a divide by 2 technique, that was not documented; (we figured it out by observing the chip's output). That chip may have been inherited by On Semiconductor. It was originally developed for some division of GE. The "dead zone problem" is less a problem and more a state of mind. :-) When implemented with a charge-pump circuit (voltage & time converter to current) between the PFD and loop filter, it rather disappears into the woodwork of the whole PLL. The phase difference between signal and reference is proportional to the control voltage of the VCO producing the basic frequency. There is ALWAYS going to be a signal versus reference phase offset when the entire loop is in lock so this dreaded "dead zone problem" will only show up in a very narrow range of controlled frequency. General intuitive thought on any PLL or other synthesizer closed loop is that the relative phase between signal and reference is zero. It isn't. If it was, then the VCO could not be controlled. As a very rough indicator of VCO frequency, that signal v. reference offset phase exists for quick scope checking...when the control voltage range of the VCO is known. Good for a quick bench check. In practical terms, that dreaded "dead zone" isn't visible in a real-world example. Case in point: 23+ years ago, Rocketdyne Division of Rockwell International (now a Division of Boeing) was beginning work on a Deformable Mirror for laser work (they had a sizeable optics group) that used a 1 MHz signal out of optics to indicate the light phase error of an optical interferometer. I rigged up a 74H family phase-frequency detector circuit as the heart of that, an integrator out of that into an A-to-D converter to get a digital version for computer data manipulation. By all the careful measurement, the expected dead zone didn't show up on any graphing and the standard lab time interval counters could resolve, accurately, 2 nanoseconds using time averaging. [translates to rather less than a degree of phase error] The optical physicists had been hopping up and down about "dead zone" in meetings but the actual circuit performance didn't show it. One reason for the non-observation of any dead zone is that the digital gates forming the PFD were so lightly loaded in other-gate capacitance that their propagation delays all tended to be the same. Datasheet values of propagation delay of gates are all given as maximums, rather worst-case things with lots of pFds connected to outputs, etc. Put on half a prototype board, loaded only by other gates of the PFD and the resistor input of an op-amp integrator, the capacitance loading was minimal. [project was successful, and spawned more work on deformable mirrors] It can be an interesting academic problem to achieve a zero dead- dead zone effect in a PFD, but thats about it. When working at the comparison frequency of less than a few MHz, the PFD dead zone due to differential propagation delays of the gates disappears into the woodwork when using 74LS or faster digital families. There's plenty to be concerned about in any frequency synthesizer subsystem, but a phase-frequency detector gate structure is a very minor problem in my opinion. DDS and fractional-N loops in synthesizers have their own problems such as spurious output, but those problems can't really be traced to any PFD dead-zone effect. A PFD is wonderful as a control loop element in that it can control a VCO (of the loop) from way off the frequency and bring it into a lock phase range...from either worst- case start-up frequency. [way back in the beginning of radio time, lock loops had to use sawtooth sweep circuits to cure that start-up condition, and couldn't control beyond +/- 90 degrees of phase shift...PFDs easily handle +/-180 degrees] Len Anderson retired (from regular hours) electronic engineer person Len - Avery, whomever, Our experiences differ. When designing PLL synths back then for two-war radio, we always saw the dead zone. "Two-war radio?" PRC-25? Term not understood. Experience has hands-on with everything from a PRC-8 to a PRC-104, but little with the PRC-25 or -77. In a type 2 loop (hope I'm remembering my control theory correctly) the extra integration allows the VCO to float around within the dead zone, causing a low freq rumble at times. You could watch the phase wandering around on a scope on the two PD inputs. If the loop is set for something like a 10 to 50 mSec lock-in time, one has to look quick to see the actual lock-in. If the loop is designed properly (VCO control voltage gain, time relative to the reference frequency), there should not be any "wander." In order to see the settling time from a large step-function of frequency change, you need to sync a scope from the step source and watch the jump-and-settle of the control voltage like a damped sinewave. That's a quick check of loop control action. Storage scope (old way) or digital scope (muy better) are the best way to view that. We would force some small leakage current just to hold it up against one side of the dead zone. Perhaps the types of requirements causes the difference. We were in the audio range with the PD reference freq and lock times in the tens of ms. if I recall correctly. Most of the older PLLs had reference frequencies of 1 to 5 KHz. That's a period of 1.0 mS to 200 uS. Without about 5 to 10 cycles for settling-in (to near invisibility), that would be about 10 to 2 mS, rather quick. If I recall, the Fairchild chip did a better job of matching the delays. The small overlap causing a narrow pulse to occur seemed like a small issue - not much energy at the ref freq for some applications. Our synthesizers were of such requirements that there was a very tight balance between lock time and spurious. The loop filtering took much care to get the lock time and keep reference spurs down. Regardless of the loop filter type, those are always fussy to avoid pickup contamination of the VCO control line. But, knowing the control voltage characteristics (delta-V v. frequency) over a range, the design is strictly textbook formula stuff. It helps greatly if the VCO control characteristics are linear versus frequency AND the division ratio maximum to minimum number is as small as possible. I've seen a few applications where both the control voltage characteristics were very non-linear AND the division ratio of the PLL greater than 2:1 with the end result being an almost impossible lock at the extreme ends of the tuning range. One case was alleviated by extra circuitry from the division control to generate a DC bias summed with the control voltage. Not too swift since it took more parts, but better than failure. In my own case, the filtering and shielding around the PFD to VCO had to be rather severe in order to keep it stable (too much high-energy circuitry rather nearby). Once that was achieved, there was no wandering at a 1 KHz reference input with proper values of known control voltage constants and accurate calculation of loop filter values. It was "tight." Len Anderson |
Everyone please read the 11C44 datasheet at:
http://ira.club.atnet.at/rd/11c44/11C44.html before declaring there is no dead zone. See figure 11. Rick N6RK "Avery Fineman" wrote in message ... In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK" writes: There are various fixes for the dead zone problem. In the mid-1970's, Fairchild (the original company) sold an "11C44" phase detector that got rid of the dead zone by injecting a narrow pulse so that the phase detector pulses would never have to try to go to zero width. Eric Breeze holds the patent on this technique; if interested read his patent. Analog Devices makes that AD9901 phase detector which gets around the dead zone by first dividing the frequency by 2. However, it is not suitable for a frequency synthesizer because of the large spurious sidebands resulting from this technique. Motorola had some patents on the circuits in its MC145159 that dealt with the dead zone and sampling sidebands. It also used a divide by 2 technique, that was not documented; (we figured it out by observing the chip's output). That chip may have been inherited by On Semiconductor. It was originally developed for some division of GE. The "dead zone problem" is less a problem and more a state of mind. :-) When implemented with a charge-pump circuit (voltage & time converter to current) between the PFD and loop filter, it rather disappears into the woodwork of the whole PLL. The phase difference between signal and reference is proportional to the control voltage of the VCO producing the basic frequency. There is ALWAYS going to be a signal versus reference phase offset when the entire loop is in lock so this dreaded "dead zone problem" will only show up in a very narrow range of controlled frequency. General intuitive thought on any PLL or other synthesizer closed loop is that the relative phase between signal and reference is zero. It isn't. If it was, then the VCO could not be controlled. As a very rough indicator of VCO frequency, that signal v. reference offset phase exists for quick scope checking...when the control voltage range of the VCO is known. Good for a quick bench check. In practical terms, that dreaded "dead zone" isn't visible in a real-world example. Case in point: 23+ years ago, Rocketdyne Division of Rockwell International (now a Division of Boeing) was beginning work on a Deformable Mirror for laser work (they had a sizeable optics group) that used a 1 MHz signal out of optics to indicate the light phase error of an optical interferometer. I rigged up a 74H family phase-frequency detector circuit as the heart of that, an integrator out of that into an A-to-D converter to get a digital version for computer data manipulation. By all the careful measurement, the expected dead zone didn't show up on any graphing and the standard lab time interval counters could resolve, accurately, 2 nanoseconds using time averaging. [translates to rather less than a degree of phase error] The optical physicists had been hopping up and down about "dead zone" in meetings but the actual circuit performance didn't show it. One reason for the non-observation of any dead zone is that the digital gates forming the PFD were so lightly loaded in other-gate capacitance that their propagation delays all tended to be the same. Datasheet values of propagation delay of gates are all given as maximums, rather worst-case things with lots of pFds connected to outputs, etc. Put on half a prototype board, loaded only by other gates of the PFD and the resistor input of an op-amp integrator, the capacitance loading was minimal. [project was successful, and spawned more work on deformable mirrors] It can be an interesting academic problem to achieve a zero dead- dead zone effect in a PFD, but thats about it. When working at the comparison frequency of less than a few MHz, the PFD dead zone due to differential propagation delays of the gates disappears into the woodwork when using 74LS or faster digital families. There's plenty to be concerned about in any frequency synthesizer subsystem, but a phase-frequency detector gate structure is a very minor problem in my opinion. DDS and fractional-N loops in synthesizers have their own problems such as spurious output, but those problems can't really be traced to any PFD dead-zone effect. A PFD is wonderful as a control loop element in that it can control a VCO (of the loop) from way off the frequency and bring it into a lock phase range...from either worst- case start-up frequency. [way back in the beginning of radio time, lock loops had to use sawtooth sweep circuits to cure that start-up condition, and couldn't control beyond +/- 90 degrees of phase shift...PFDs easily handle +/-180 degrees] Len Anderson retired (from regular hours) electronic engineer person |
Everyone please read the 11C44 datasheet at:
http://ira.club.atnet.at/rd/11c44/11C44.html before declaring there is no dead zone. See figure 11. Rick N6RK "Avery Fineman" wrote in message ... In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK" writes: There are various fixes for the dead zone problem. In the mid-1970's, Fairchild (the original company) sold an "11C44" phase detector that got rid of the dead zone by injecting a narrow pulse so that the phase detector pulses would never have to try to go to zero width. Eric Breeze holds the patent on this technique; if interested read his patent. Analog Devices makes that AD9901 phase detector which gets around the dead zone by first dividing the frequency by 2. However, it is not suitable for a frequency synthesizer because of the large spurious sidebands resulting from this technique. Motorola had some patents on the circuits in its MC145159 that dealt with the dead zone and sampling sidebands. It also used a divide by 2 technique, that was not documented; (we figured it out by observing the chip's output). That chip may have been inherited by On Semiconductor. It was originally developed for some division of GE. The "dead zone problem" is less a problem and more a state of mind. :-) When implemented with a charge-pump circuit (voltage & time converter to current) between the PFD and loop filter, it rather disappears into the woodwork of the whole PLL. The phase difference between signal and reference is proportional to the control voltage of the VCO producing the basic frequency. There is ALWAYS going to be a signal versus reference phase offset when the entire loop is in lock so this dreaded "dead zone problem" will only show up in a very narrow range of controlled frequency. General intuitive thought on any PLL or other synthesizer closed loop is that the relative phase between signal and reference is zero. It isn't. If it was, then the VCO could not be controlled. As a very rough indicator of VCO frequency, that signal v. reference offset phase exists for quick scope checking...when the control voltage range of the VCO is known. Good for a quick bench check. In practical terms, that dreaded "dead zone" isn't visible in a real-world example. Case in point: 23+ years ago, Rocketdyne Division of Rockwell International (now a Division of Boeing) was beginning work on a Deformable Mirror for laser work (they had a sizeable optics group) that used a 1 MHz signal out of optics to indicate the light phase error of an optical interferometer. I rigged up a 74H family phase-frequency detector circuit as the heart of that, an integrator out of that into an A-to-D converter to get a digital version for computer data manipulation. By all the careful measurement, the expected dead zone didn't show up on any graphing and the standard lab time interval counters could resolve, accurately, 2 nanoseconds using time averaging. [translates to rather less than a degree of phase error] The optical physicists had been hopping up and down about "dead zone" in meetings but the actual circuit performance didn't show it. One reason for the non-observation of any dead zone is that the digital gates forming the PFD were so lightly loaded in other-gate capacitance that their propagation delays all tended to be the same. Datasheet values of propagation delay of gates are all given as maximums, rather worst-case things with lots of pFds connected to outputs, etc. Put on half a prototype board, loaded only by other gates of the PFD and the resistor input of an op-amp integrator, the capacitance loading was minimal. [project was successful, and spawned more work on deformable mirrors] It can be an interesting academic problem to achieve a zero dead- dead zone effect in a PFD, but thats about it. When working at the comparison frequency of less than a few MHz, the PFD dead zone due to differential propagation delays of the gates disappears into the woodwork when using 74LS or faster digital families. There's plenty to be concerned about in any frequency synthesizer subsystem, but a phase-frequency detector gate structure is a very minor problem in my opinion. DDS and fractional-N loops in synthesizers have their own problems such as spurious output, but those problems can't really be traced to any PFD dead-zone effect. A PFD is wonderful as a control loop element in that it can control a VCO (of the loop) from way off the frequency and bring it into a lock phase range...from either worst- case start-up frequency. [way back in the beginning of radio time, lock loops had to use sawtooth sweep circuits to cure that start-up condition, and couldn't control beyond +/- 90 degrees of phase shift...PFDs easily handle +/-180 degrees] Len Anderson retired (from regular hours) electronic engineer person |
Let me try again to explain dead zone.
Many PLL's never experience the dead zone because the loop filter is constructed using op amps with high (10 mV) offset voltage specs. This offset forces the loop to lock up outside the dead zone. If you use a low offset op amp, and then put in an offset adjust pot to take out any residual offset from the phase detector, you can observe the spurious sidebands at the phase detection frequency null out. However, you will then find that the loop bandwidth has changed substantially, because you are in the dead zone region. The VCO will get more phase noise because the loop wanders around (like a bang-bang loop) in the dead zone, and/or the change in loop bandwidth has de-optimized the suppression of VCO noise by the PLL. I have personally observed this and other engineers I have mentored have also observed it (after first arguing with me that it wouldn't happen). By the way, the pot tweaking to null sidebands doesn't hold over temperature (no surprise) so it's still bogus even without the dead zone issue. To correct previous misinformation about the 11C44: the gates are not better matched; rather there is an extra pulse injection circuit as described in Eric Breeze's patent. This information is from a conversion with Eric Breeze 28 years ago. The 11C44 hasn't been available for many years but that was due to mismanagement of Fairchild (which was bought by National) rather than lack of merit of the 11C44. (There was a lot of great technology at Fairchild screwed up by mismanagement). Rick N6RK "Avery Fineman" wrote in message ... In article , "W3JDR" writes: Dead-zone = phase noise. Very little dead-zone = very little phase noise. Bigger dead-zone = bigger phase noise. You can interpolate the rest for yourself. I have to disagree with some of that. First of all, a "dead zone" or the almost-exactly-in-phase condition, occurs at only one VCO frequency where the control voltage sets up the frequency for that in-phase condition. Yes, at that exact frequency, there COULD be some phase noise. But, the phase noise may NOT be from this "dead zone" effect. Phase noise can come from MANY different sources. If it occurs well away from the in-same-phase "dead zone" then the phase noise is NOT caused by any "dead zone." The relative phase between signal and reference inputs to a PFD correspond to the VCO control voltage (times the charge-pump or integrator circuit constants). Signal and reference phases when in lock will always be offset from one another, one leading and one lagging. A good loop will show a constant offset of phases even when both inputs hold a constant phase. Len Anderson |
Let me try again to explain dead zone.
Many PLL's never experience the dead zone because the loop filter is constructed using op amps with high (10 mV) offset voltage specs. This offset forces the loop to lock up outside the dead zone. If you use a low offset op amp, and then put in an offset adjust pot to take out any residual offset from the phase detector, you can observe the spurious sidebands at the phase detection frequency null out. However, you will then find that the loop bandwidth has changed substantially, because you are in the dead zone region. The VCO will get more phase noise because the loop wanders around (like a bang-bang loop) in the dead zone, and/or the change in loop bandwidth has de-optimized the suppression of VCO noise by the PLL. I have personally observed this and other engineers I have mentored have also observed it (after first arguing with me that it wouldn't happen). By the way, the pot tweaking to null sidebands doesn't hold over temperature (no surprise) so it's still bogus even without the dead zone issue. To correct previous misinformation about the 11C44: the gates are not better matched; rather there is an extra pulse injection circuit as described in Eric Breeze's patent. This information is from a conversion with Eric Breeze 28 years ago. The 11C44 hasn't been available for many years but that was due to mismanagement of Fairchild (which was bought by National) rather than lack of merit of the 11C44. (There was a lot of great technology at Fairchild screwed up by mismanagement). Rick N6RK "Avery Fineman" wrote in message ... In article , "W3JDR" writes: Dead-zone = phase noise. Very little dead-zone = very little phase noise. Bigger dead-zone = bigger phase noise. You can interpolate the rest for yourself. I have to disagree with some of that. First of all, a "dead zone" or the almost-exactly-in-phase condition, occurs at only one VCO frequency where the control voltage sets up the frequency for that in-phase condition. Yes, at that exact frequency, there COULD be some phase noise. But, the phase noise may NOT be from this "dead zone" effect. Phase noise can come from MANY different sources. If it occurs well away from the in-same-phase "dead zone" then the phase noise is NOT caused by any "dead zone." The relative phase between signal and reference inputs to a PFD correspond to the VCO control voltage (times the charge-pump or integrator circuit constants). Signal and reference phases when in lock will always be offset from one another, one leading and one lagging. A good loop will show a constant offset of phases even when both inputs hold a constant phase. Len Anderson |
If you build a PLL with a low offset op amp (not the usual
ones with 10 mV offset spec) and then use a pot to tweak out the residual phase detector output offset voltage, you will see the sidebands on the VCO null out at a certain setting of the pot. At this setting, you will typically be in or near the dead zone. Although the spurious sidebands are impressively low, the loop bandwidth will now be unpredictable, which may de-optimize the phase noise. Also, there may be a lot of low frequency residual FM on the VCO because the loop is acting like a bang bang loop. Many engineers have never seen this happen, because it is unlikely to happen by accident. BTW, the pot setting won't hold very well over temperature. Rick N6RK "Avery Fineman" wrote in message ... In article , "W3JDR" writes: Dead-zone = phase noise. Very little dead-zone = very little phase noise. Bigger dead-zone = bigger phase noise. You can interpolate the rest for yourself. I have to disagree with some of that. First of all, a "dead zone" or the almost-exactly-in-phase condition, occurs at only one VCO frequency where the control voltage sets up the frequency for that in-phase condition. Yes, at that exact frequency, there COULD be some phase noise. But, the phase noise may NOT be from this "dead zone" effect. Phase noise can come from MANY different sources. If it occurs well away from the in-same-phase "dead zone" then the phase noise is NOT caused by any "dead zone." The relative phase between signal and reference inputs to a PFD correspond to the VCO control voltage (times the charge-pump or integrator circuit constants). Signal and reference phases when in lock will always be offset from one another, one leading and one lagging. A good loop will show a constant offset of phases even when both inputs hold a constant phase. Len Anderson |
If you build a PLL with a low offset op amp (not the usual
ones with 10 mV offset spec) and then use a pot to tweak out the residual phase detector output offset voltage, you will see the sidebands on the VCO null out at a certain setting of the pot. At this setting, you will typically be in or near the dead zone. Although the spurious sidebands are impressively low, the loop bandwidth will now be unpredictable, which may de-optimize the phase noise. Also, there may be a lot of low frequency residual FM on the VCO because the loop is acting like a bang bang loop. Many engineers have never seen this happen, because it is unlikely to happen by accident. BTW, the pot setting won't hold very well over temperature. Rick N6RK "Avery Fineman" wrote in message ... In article , "W3JDR" writes: Dead-zone = phase noise. Very little dead-zone = very little phase noise. Bigger dead-zone = bigger phase noise. You can interpolate the rest for yourself. I have to disagree with some of that. First of all, a "dead zone" or the almost-exactly-in-phase condition, occurs at only one VCO frequency where the control voltage sets up the frequency for that in-phase condition. Yes, at that exact frequency, there COULD be some phase noise. But, the phase noise may NOT be from this "dead zone" effect. Phase noise can come from MANY different sources. If it occurs well away from the in-same-phase "dead zone" then the phase noise is NOT caused by any "dead zone." The relative phase between signal and reference inputs to a PFD correspond to the VCO control voltage (times the charge-pump or integrator circuit constants). Signal and reference phases when in lock will always be offset from one another, one leading and one lagging. A good loop will show a constant offset of phases even when both inputs hold a constant phase. Len Anderson |
In article bWTtc.11435$eY2.451@attbi_s02, "Rick Karlquist N6RK"
writes: Let me try again to explain dead zone. Many PLL's never experience the dead zone because the loop filter is constructed using op amps with high (10 mV) offset voltage specs. This offset forces the loop to lock up outside the dead zone. With any phase-frequency detector, the width of the output rectangular wave (from the digital portion) is proportional to the control voltage output. That width can be converted to a DC control voltage by a charge pump (pins 4, 5, 10, 11 in either the MC4044 or 11C44 package) or done externally in an integrator such as with an op-amp. When locked, the signal and reference inputs of the PFD will be in-phase but the relative phases are offset in time. It is that offset which eventually produces the control voltage that brings the VCO into the in-phase condition. A "dead zone" does indeed exist in all such circuits but it will take effect ONLY in the VCO frequency region where the phases of signal and reference input are the same or very nearly the same. At any other VCO frequency the "dead zone" has no effect since the phase offsets of signal and reference are away from that "dead zone." Note: The signal and reference phases will be "in-phase" meaning that they are both on the same frequency but the signal is offset in phase from the reference. The "offset" of any extra circuit elements to an op-amp used in coupling the PFD to the VCO can be used as a stop-gap cure for the "dead-zone" but that still is effective only in the phase relationship of the signal v. reference inputs where they are nearly the same phase. If you use a low offset op amp, and then put in an offset adjust pot to take out any residual offset from the phase detector, you can observe the spurious sidebands at the phase detection frequency null out. Observation shows the entirety of the loop action. It does not pin down a cause of the spurious outputs. Those spurious outputs can be caused by a number of different things. However, you will then find that the loop bandwidth has changed substantially, because you are in the dead zone region. The VCO will get more phase noise because the loop wanders around (like a bang-bang loop) in the dead zone, and/or the change in loop bandwidth has de-optimized the suppression of VCO noise by the PLL. The VCO control voltage curve sets part of the loop filter's frequency response and is called the "gain" of the loop feedback. Bandwidth is dependent primarily by the reference frequency plus the lock-in response time desired. Too much "gain" and the whole loop goes into oscillation, never settling down; too little and the loop takes a very long time to lock in (and may never do so). Curvature of the slope of the PFD output (converted from time to voltage) affects the "gain" and thus the total closed-loop condition. I have personally observed this and other engineers I have mentored have also observed it (after first arguing with me that it wouldn't happen). The "dead zone" does indeed exist but I'm simply saying that (1). It isn't an ogre ready to strike fear in use; (2). It doesn't effect a PLL lock over all VCO frequencies...just that narrow range of VCO frequencies where the relative phase offsets of the signal and reference inputs to the PFD are about the same. The original question involved a six 2-input, two 3-input, and (one 4-input) gate EQUIVALENT of the '44. That original '44 design is an elegant one, a sort of gigantic flip-flop on steroids which will work over a +/-180 degree range. It is far superior to the old types of phase detectors which had only a +/- 90 degree operating range. The time characteristics (or phase relationship of input rectangular signals) of such a circuit can be much improved by using faster-responding digital logic families. By using 74F or 74H or other very fast gates, the "dead zone" can be made very small, enough to essentially forget about any such effects on the overall PLL with a 10 KHz or lower reference frequency. If there is anxiety over the PFD operation, it can be examined with a 'scope and a stable, delayed signal pulse synced from the reference input. The '44 circuit type doesn't need square waves but can operate solely on leading edges. With a time- interval-averaging counter, the signal input phase can be set/ characterized very accurately as well as the output pulse width. Lacking a time counter, a 'scope (hopefully with delayed time base function) can be used for coarser measurement. The 'scope will display the "dead zone" condition. To correct previous misinformation about the 11C44: the gates are not better matched; rather there is an extra pulse injection circuit as described in Eric Breeze's patent. That's not included in the diagram shown on the 11C44 data sheet website you referenced. That gate diagram and charge pump and Darlington bipolar circuits are exactly as in the original Motorola '44 data sheet. Either PFD gate arrangement can be duplicated using "discrete" logic gates. In my opinion there's an elegant simplicity of the '44 gate arrangement which adequately fulfills its purpose of not only operating over a +/- 180 degree input phase offset but also staying on extremes of low or high frequency signal input condition, ideal for PLL start-up. I'd like to know the original circuit designer to send thanks for such elegance in circuitry. Other manufacturers (such as RCA and Intersil) have duplicated the '44 PFD gate arrangement with success. It can be copied with ordinary logic gates without problem. If there is a region of a PLL to concentrate on, I'd say it is in the pulse width to DC control voltage following circuit and the loop filter (and its shielding and isolation). Len Anderson retired (from regular hours) electronic engineer person |
In article bWTtc.11435$eY2.451@attbi_s02, "Rick Karlquist N6RK"
writes: Let me try again to explain dead zone. Many PLL's never experience the dead zone because the loop filter is constructed using op amps with high (10 mV) offset voltage specs. This offset forces the loop to lock up outside the dead zone. With any phase-frequency detector, the width of the output rectangular wave (from the digital portion) is proportional to the control voltage output. That width can be converted to a DC control voltage by a charge pump (pins 4, 5, 10, 11 in either the MC4044 or 11C44 package) or done externally in an integrator such as with an op-amp. When locked, the signal and reference inputs of the PFD will be in-phase but the relative phases are offset in time. It is that offset which eventually produces the control voltage that brings the VCO into the in-phase condition. A "dead zone" does indeed exist in all such circuits but it will take effect ONLY in the VCO frequency region where the phases of signal and reference input are the same or very nearly the same. At any other VCO frequency the "dead zone" has no effect since the phase offsets of signal and reference are away from that "dead zone." Note: The signal and reference phases will be "in-phase" meaning that they are both on the same frequency but the signal is offset in phase from the reference. The "offset" of any extra circuit elements to an op-amp used in coupling the PFD to the VCO can be used as a stop-gap cure for the "dead-zone" but that still is effective only in the phase relationship of the signal v. reference inputs where they are nearly the same phase. If you use a low offset op amp, and then put in an offset adjust pot to take out any residual offset from the phase detector, you can observe the spurious sidebands at the phase detection frequency null out. Observation shows the entirety of the loop action. It does not pin down a cause of the spurious outputs. Those spurious outputs can be caused by a number of different things. However, you will then find that the loop bandwidth has changed substantially, because you are in the dead zone region. The VCO will get more phase noise because the loop wanders around (like a bang-bang loop) in the dead zone, and/or the change in loop bandwidth has de-optimized the suppression of VCO noise by the PLL. The VCO control voltage curve sets part of the loop filter's frequency response and is called the "gain" of the loop feedback. Bandwidth is dependent primarily by the reference frequency plus the lock-in response time desired. Too much "gain" and the whole loop goes into oscillation, never settling down; too little and the loop takes a very long time to lock in (and may never do so). Curvature of the slope of the PFD output (converted from time to voltage) affects the "gain" and thus the total closed-loop condition. I have personally observed this and other engineers I have mentored have also observed it (after first arguing with me that it wouldn't happen). The "dead zone" does indeed exist but I'm simply saying that (1). It isn't an ogre ready to strike fear in use; (2). It doesn't effect a PLL lock over all VCO frequencies...just that narrow range of VCO frequencies where the relative phase offsets of the signal and reference inputs to the PFD are about the same. The original question involved a six 2-input, two 3-input, and (one 4-input) gate EQUIVALENT of the '44. That original '44 design is an elegant one, a sort of gigantic flip-flop on steroids which will work over a +/-180 degree range. It is far superior to the old types of phase detectors which had only a +/- 90 degree operating range. The time characteristics (or phase relationship of input rectangular signals) of such a circuit can be much improved by using faster-responding digital logic families. By using 74F or 74H or other very fast gates, the "dead zone" can be made very small, enough to essentially forget about any such effects on the overall PLL with a 10 KHz or lower reference frequency. If there is anxiety over the PFD operation, it can be examined with a 'scope and a stable, delayed signal pulse synced from the reference input. The '44 circuit type doesn't need square waves but can operate solely on leading edges. With a time- interval-averaging counter, the signal input phase can be set/ characterized very accurately as well as the output pulse width. Lacking a time counter, a 'scope (hopefully with delayed time base function) can be used for coarser measurement. The 'scope will display the "dead zone" condition. To correct previous misinformation about the 11C44: the gates are not better matched; rather there is an extra pulse injection circuit as described in Eric Breeze's patent. That's not included in the diagram shown on the 11C44 data sheet website you referenced. That gate diagram and charge pump and Darlington bipolar circuits are exactly as in the original Motorola '44 data sheet. Either PFD gate arrangement can be duplicated using "discrete" logic gates. In my opinion there's an elegant simplicity of the '44 gate arrangement which adequately fulfills its purpose of not only operating over a +/- 180 degree input phase offset but also staying on extremes of low or high frequency signal input condition, ideal for PLL start-up. I'd like to know the original circuit designer to send thanks for such elegance in circuitry. Other manufacturers (such as RCA and Intersil) have duplicated the '44 PFD gate arrangement with success. It can be copied with ordinary logic gates without problem. If there is a region of a PLL to concentrate on, I'd say it is in the pulse width to DC control voltage following circuit and the loop filter (and its shielding and isolation). Len Anderson retired (from regular hours) electronic engineer person |
I'd like to know the original
circuit designer to send thanks for such elegance in circuitry. I've never been able to find any historical reference to the MC4044 designer. It seems to be one of those lost pieces of history. Rick N6RK |
I'd like to know the original
circuit designer to send thanks for such elegance in circuitry. I've never been able to find any historical reference to the MC4044 designer. It seems to be one of those lost pieces of history. Rick N6RK |
"Rick Karlquist N6RK" ) writes:
I'd like to know the original circuit designer to send thanks for such elegance in circuitry. I've never been able to find any historical reference to the MC4044 designer. It seems to be one of those lost pieces of history. Rick N6RK It's Jim Thompson, over in sci.electronics.design He did some other famous ICs, like the MC1488 and MC1489 RS-232 pair, and I believe he did the MC1468 ECL VCO. Michael VE2BVW |
"Rick Karlquist N6RK" ) writes:
I'd like to know the original circuit designer to send thanks for such elegance in circuitry. I've never been able to find any historical reference to the MC4044 designer. It seems to be one of those lost pieces of history. Rick N6RK It's Jim Thompson, over in sci.electronics.design He did some other famous ICs, like the MC1488 and MC1489 RS-232 pair, and I believe he did the MC1468 ECL VCO. Michael VE2BVW |
Rick Karlquist N6RK wrote:
I'd like to know the original circuit designer to send thanks for such elegance in circuitry. I've never been able to find any historical reference to the MC4044 designer. It seems to be one of those lost pieces of history. Rick N6RK There is a discussion on sci.electronics.design on this same subject (spawned by Deepthi as well). Turns out that one of the regulars over there, Jim Thompson, is 1/2 of the designer of this part, and the 12xxx series replacement for it. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com |
Rick Karlquist N6RK wrote:
I'd like to know the original circuit designer to send thanks for such elegance in circuitry. I've never been able to find any historical reference to the MC4044 designer. It seems to be one of those lost pieces of history. Rick N6RK There is a discussion on sci.electronics.design on this same subject (spawned by Deepthi as well). Turns out that one of the regulars over there, Jim Thompson, is 1/2 of the designer of this part, and the 12xxx series replacement for it. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com |
Thanks.....QSY'ing to sci.electronics
"Michael Black" wrote in message ... "Rick Karlquist N6RK" ) writes: I'd like to know the original circuit designer to send thanks for such elegance in circuitry. I've never been able to find any historical reference to the MC4044 designer. It seems to be one of those lost pieces of history. Rick N6RK It's Jim Thompson, over in sci.electronics.design He did some other famous ICs, like the MC1488 and MC1489 RS-232 pair, and I believe he did the MC1468 ECL VCO. Michael VE2BVW |
Thanks.....QSY'ing to sci.electronics
"Michael Black" wrote in message ... "Rick Karlquist N6RK" ) writes: I'd like to know the original circuit designer to send thanks for such elegance in circuitry. I've never been able to find any historical reference to the MC4044 designer. It seems to be one of those lost pieces of history. Rick N6RK It's Jim Thompson, over in sci.electronics.design He did some other famous ICs, like the MC1488 and MC1489 RS-232 pair, and I believe he did the MC1468 ECL VCO. Michael VE2BVW |
Hello All
Rick Karlquist. N6RK, on 5/28/04 wrote: Everyone please read the 11C44 datasheet at: http://ira.club.atnet.at/rd/11c44/11C44.html before declaring there is no dead zone. See figure 11. Rick N6RK "Avery Fineman" wrote in message ... In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK" writes: There are various fixes for the dead zone problem. In the mid-1970's, Fairchild (the original company) sold an "11C44" phase detector that got rid of the dead zone by injecting a narrow pulse so that the phase detector pulses would never have to try to go to zero width. Eric Breeze holds the patent on this technique; if interested read his patent. Analog Devices makes that AD9901 phase detector which gets around the dead zone by first dividing the frequency by 2. However, it is not suitable for a frequency synthesizer because of the large spurious sidebands resulting from this technique. SNIP See also 'The PLL Dead Zone and How to Avoid it', A. Hill & J. Surber, RF Design, March 1992, pp131-134. The authors were with Analog Devices and compared the performance of the AD9901 with that of the MC4044. My understanding of the AD9901 is that it behaves as a edge controlled frequency detector, until it gets close enough in frequency, when it switches to being an EXOR phase detector. I am struggling to understand the comment above that the AD9901 is not suitable for use in frequency synthesisers because of the large spurious sidebands arising from its use. What causes the additional sidebands ? Elsewhere in this thread there seems to have been some debate on the operation of the phase frequency detector. IMHO if the phase detector has a tri-state output then the loop over time must lock with no phase difference between the reference and controlled signals, ie 0 degrees. 73 John KC0GGH |
Hello All
Rick Karlquist. N6RK, on 5/28/04 wrote: Everyone please read the 11C44 datasheet at: http://ira.club.atnet.at/rd/11c44/11C44.html before declaring there is no dead zone. See figure 11. Rick N6RK "Avery Fineman" wrote in message ... In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK" writes: There are various fixes for the dead zone problem. In the mid-1970's, Fairchild (the original company) sold an "11C44" phase detector that got rid of the dead zone by injecting a narrow pulse so that the phase detector pulses would never have to try to go to zero width. Eric Breeze holds the patent on this technique; if interested read his patent. Analog Devices makes that AD9901 phase detector which gets around the dead zone by first dividing the frequency by 2. However, it is not suitable for a frequency synthesizer because of the large spurious sidebands resulting from this technique. SNIP See also 'The PLL Dead Zone and How to Avoid it', A. Hill & J. Surber, RF Design, March 1992, pp131-134. The authors were with Analog Devices and compared the performance of the AD9901 with that of the MC4044. My understanding of the AD9901 is that it behaves as a edge controlled frequency detector, until it gets close enough in frequency, when it switches to being an EXOR phase detector. I am struggling to understand the comment above that the AD9901 is not suitable for use in frequency synthesisers because of the large spurious sidebands arising from its use. What causes the additional sidebands ? Elsewhere in this thread there seems to have been some debate on the operation of the phase frequency detector. IMHO if the phase detector has a tri-state output then the loop over time must lock with no phase difference between the reference and controlled signals, ie 0 degrees. 73 John KC0GGH |
John,
Elsewhere in this thread there seems to have been some debate on the operation of the phase frequency detector. IMHO if the phase detector has a tri-state output then the loop over time must lock with no phase difference between the reference and controlled signals, ie 0 degrees. Theoretically, the edge controlled PFD locks the signal & reference with 0 degrees phase error. When the loop is locked, the output pulses from the PFD are theoretically infinitesimally small. However, neither the PFD chip nor the external charge pump/loop filter are perfect. Any leakage in the charge pump and/or loop filter causes the PFD to continually output wider than normal pulses in order to supply the additional charge current necessary to make up for the current leakage. This results in a non-zero phase error at the PFD inputs. I am struggling to understand the comment above that the AD9901 is not suitable for use in frequency synthesizers because of the large spurious sidebands arising from its use. What causes the additional sidebands ? As mentioned, the PFD output pulses approach zero width at lock, making it easier to filter the pulses down to pure DC in the charge pump/loop filter. The XOR PD will output a 50% duty cycle pulse train at lock. This is much more difficult to filter down to pure DC, resulting in modulation of the VCO, and thus sidebands. Joe W3JDR "John Crabtree" wrote in message ... Hello All Rick Karlquist. N6RK, on 5/28/04 wrote: Everyone please read the 11C44 datasheet at: http://ira.club.atnet.at/rd/11c44/11C44.html before declaring there is no dead zone. See figure 11. Rick N6RK "Avery Fineman" wrote in message ... In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK" writes: There are various fixes for the dead zone problem. In the mid-1970's, Fairchild (the original company) sold an "11C44" phase detector that got rid of the dead zone by injecting a narrow pulse so that the phase detector pulses would never have to try to go to zero width. Eric Breeze holds the patent on this technique; if interested read his patent. Analog Devices makes that AD9901 phase detector which gets around the dead zone by first dividing the frequency by 2. However, it is not suitable for a frequency synthesizer because of the large spurious sidebands resulting from this technique. SNIP See also 'The PLL Dead Zone and How to Avoid it', A. Hill & J. Surber, RF Design, March 1992, pp131-134. The authors were with Analog Devices and compared the performance of the AD9901 with that of the MC4044. My understanding of the AD9901 is that it behaves as a edge controlled frequency detector, until it gets close enough in frequency, when it switches to being an EXOR phase detector. I am struggling to understand the comment above that the AD9901 is not suitable for use in frequency synthesisers because of the large spurious sidebands arising from its use. What causes the additional sidebands ? Elsewhere in this thread there seems to have been some debate on the operation of the phase frequency detector. IMHO if the phase detector has a tri-state output then the loop over time must lock with no phase difference between the reference and controlled signals, ie 0 degrees. 73 John KC0GGH |
John,
Elsewhere in this thread there seems to have been some debate on the operation of the phase frequency detector. IMHO if the phase detector has a tri-state output then the loop over time must lock with no phase difference between the reference and controlled signals, ie 0 degrees. Theoretically, the edge controlled PFD locks the signal & reference with 0 degrees phase error. When the loop is locked, the output pulses from the PFD are theoretically infinitesimally small. However, neither the PFD chip nor the external charge pump/loop filter are perfect. Any leakage in the charge pump and/or loop filter causes the PFD to continually output wider than normal pulses in order to supply the additional charge current necessary to make up for the current leakage. This results in a non-zero phase error at the PFD inputs. I am struggling to understand the comment above that the AD9901 is not suitable for use in frequency synthesizers because of the large spurious sidebands arising from its use. What causes the additional sidebands ? As mentioned, the PFD output pulses approach zero width at lock, making it easier to filter the pulses down to pure DC in the charge pump/loop filter. The XOR PD will output a 50% duty cycle pulse train at lock. This is much more difficult to filter down to pure DC, resulting in modulation of the VCO, and thus sidebands. Joe W3JDR "John Crabtree" wrote in message ... Hello All Rick Karlquist. N6RK, on 5/28/04 wrote: Everyone please read the 11C44 datasheet at: http://ira.club.atnet.at/rd/11c44/11C44.html before declaring there is no dead zone. See figure 11. Rick N6RK "Avery Fineman" wrote in message ... In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK" writes: There are various fixes for the dead zone problem. In the mid-1970's, Fairchild (the original company) sold an "11C44" phase detector that got rid of the dead zone by injecting a narrow pulse so that the phase detector pulses would never have to try to go to zero width. Eric Breeze holds the patent on this technique; if interested read his patent. Analog Devices makes that AD9901 phase detector which gets around the dead zone by first dividing the frequency by 2. However, it is not suitable for a frequency synthesizer because of the large spurious sidebands resulting from this technique. SNIP See also 'The PLL Dead Zone and How to Avoid it', A. Hill & J. Surber, RF Design, March 1992, pp131-134. The authors were with Analog Devices and compared the performance of the AD9901 with that of the MC4044. My understanding of the AD9901 is that it behaves as a edge controlled frequency detector, until it gets close enough in frequency, when it switches to being an EXOR phase detector. I am struggling to understand the comment above that the AD9901 is not suitable for use in frequency synthesisers because of the large spurious sidebands arising from its use. What causes the additional sidebands ? Elsewhere in this thread there seems to have been some debate on the operation of the phase frequency detector. IMHO if the phase detector has a tri-state output then the loop over time must lock with no phase difference between the reference and controlled signals, ie 0 degrees. 73 John KC0GGH |
In article , "W3JDR"
writes: John, Elsewhere in this thread there seems to have been some debate on the operation of the phase frequency detector. IMHO if the phase detector has a tri-state output then the loop over time must lock with no phase difference between the reference and controlled signals, ie 0 degrees. Theoretically, the edge controlled PFD locks the signal & reference with 0 degrees phase error. When the loop is locked, the output pulses from the PFD are theoretically infinitesimally small. However, neither the PFD chip nor the external charge pump/loop filter are perfect. Any leakage in the charge pump and/or loop filter causes the PFD to continually output wider than normal pulses in order to supply the additional charge current necessary to make up for the current leakage. This results in a non-zero phase error at the PFD inputs. Not quite it. In order to derive a control voltage for the controlled oscillator, the PFD output MUST BE A FINITE WIDTH. In lock, at any frequency increment, the relative phase of the signal and reference is constant, stable, BUT THERE IS ALWAYS A PHASE OFFSET. This is necessary in order to derive the control voltage which keeps the VCO in lock. It's a common misconception to think of phase lock or even phase control as trying to achieve a "zero degree" condition with no phase offset. What is achieved in phase lock is a STABLE, BUT OFFSET, phase relationship between signal and reference frequencies at PFD inputs. The easiest way to prove the condition is to scope an adjustable- frequency PLL at the signal and reference PFD inputs and then the '44-type PFD output into the loop filter. [measure the VCO frequency separately if desired to prove the VCO, if desired] At one locked frequency of the VCO the PFD output is a finite-width pulse at the reference frequency. Change the divider setting for a new VCO frequency and the PFD output has a different pulse width. That can be confirmed by the DC control voltage...one value at the first frequency setting, another value at the second frequency setting. That DC control voltage is, in effect, an average value of the pulse width out of the PFD. I am struggling to understand the comment above that the AD9901 is not suitable for use in frequency synthesizers because of the large spurious sidebands arising from its use. What causes the additional sidebands ? As mentioned, the PFD output pulses approach zero width at lock, making it easier to filter the pulses down to pure DC in the charge pump/loop filter. No. In the '44-type PFD, the output pulses will be zero ONLY if the divided VCO is way off frequency, at one end of the controllable range or the other. IN LOCK the PFD output will ALWAYS HAVE A FINITE PULSE WIDTH at the reference frequency repetition rate. Without that pulse width averaged out there would be NO control voltage to hold the divided VCO within range. The XOR PD will output a 50% duty cycle pulse train at lock. This is much more difficult to filter down to pure DC, resulting in modulation of the VCO, and thus sidebands. It is no different. Control voltage averaged out of an XOR phase detector is still from essentially the same finite pulse width. [those have worked for years without any comments about "spurs"] The vast difference between an XOR PD and the '44-type PFD is that the XOR PD is limited to a +/- 90 degree control and can't tell the loop how to come off of a start-up condition which is way off to one side of the VCO range or the other. The '44-type PFD works over +/- 180 degree range and DOES indicate a way-off VCO signal frequency condition. It will start up safely. In the old PDs limited to 90 degree range, the general way of starting up was with a very slow sawtooth generator algebraically adding to the control voltage...once the lock range was achieved, more circuitry shut off the sawtooth. [lots of extra parts] In either type of phase detector, the amount of reference frequency ripple out of the loop filter is dependent on the type of filter and the speed of lock-in time on changing frequency of the VCO through the divider setting. On can make the loop filter very slow and cut the (awful, terrible) spurious sidebands down...and also waste literal minutes waiting for the PLL to lock in. Those (awful, terrible) spurs at increments of the reference frequency are seldom worth worrying about in a PLL with good shielding and decoupling around the control voltage parts of the PLL. [the proof lies in tens of thousands of simple PLLs working all around the globe without worries over "not working" because their spurious outputs are "too high"] Len Anderson retired (from regular hours) electronic engineer person |
In article , "W3JDR"
writes: John, Elsewhere in this thread there seems to have been some debate on the operation of the phase frequency detector. IMHO if the phase detector has a tri-state output then the loop over time must lock with no phase difference between the reference and controlled signals, ie 0 degrees. Theoretically, the edge controlled PFD locks the signal & reference with 0 degrees phase error. When the loop is locked, the output pulses from the PFD are theoretically infinitesimally small. However, neither the PFD chip nor the external charge pump/loop filter are perfect. Any leakage in the charge pump and/or loop filter causes the PFD to continually output wider than normal pulses in order to supply the additional charge current necessary to make up for the current leakage. This results in a non-zero phase error at the PFD inputs. Not quite it. In order to derive a control voltage for the controlled oscillator, the PFD output MUST BE A FINITE WIDTH. In lock, at any frequency increment, the relative phase of the signal and reference is constant, stable, BUT THERE IS ALWAYS A PHASE OFFSET. This is necessary in order to derive the control voltage which keeps the VCO in lock. It's a common misconception to think of phase lock or even phase control as trying to achieve a "zero degree" condition with no phase offset. What is achieved in phase lock is a STABLE, BUT OFFSET, phase relationship between signal and reference frequencies at PFD inputs. The easiest way to prove the condition is to scope an adjustable- frequency PLL at the signal and reference PFD inputs and then the '44-type PFD output into the loop filter. [measure the VCO frequency separately if desired to prove the VCO, if desired] At one locked frequency of the VCO the PFD output is a finite-width pulse at the reference frequency. Change the divider setting for a new VCO frequency and the PFD output has a different pulse width. That can be confirmed by the DC control voltage...one value at the first frequency setting, another value at the second frequency setting. That DC control voltage is, in effect, an average value of the pulse width out of the PFD. I am struggling to understand the comment above that the AD9901 is not suitable for use in frequency synthesizers because of the large spurious sidebands arising from its use. What causes the additional sidebands ? As mentioned, the PFD output pulses approach zero width at lock, making it easier to filter the pulses down to pure DC in the charge pump/loop filter. No. In the '44-type PFD, the output pulses will be zero ONLY if the divided VCO is way off frequency, at one end of the controllable range or the other. IN LOCK the PFD output will ALWAYS HAVE A FINITE PULSE WIDTH at the reference frequency repetition rate. Without that pulse width averaged out there would be NO control voltage to hold the divided VCO within range. The XOR PD will output a 50% duty cycle pulse train at lock. This is much more difficult to filter down to pure DC, resulting in modulation of the VCO, and thus sidebands. It is no different. Control voltage averaged out of an XOR phase detector is still from essentially the same finite pulse width. [those have worked for years without any comments about "spurs"] The vast difference between an XOR PD and the '44-type PFD is that the XOR PD is limited to a +/- 90 degree control and can't tell the loop how to come off of a start-up condition which is way off to one side of the VCO range or the other. The '44-type PFD works over +/- 180 degree range and DOES indicate a way-off VCO signal frequency condition. It will start up safely. In the old PDs limited to 90 degree range, the general way of starting up was with a very slow sawtooth generator algebraically adding to the control voltage...once the lock range was achieved, more circuitry shut off the sawtooth. [lots of extra parts] In either type of phase detector, the amount of reference frequency ripple out of the loop filter is dependent on the type of filter and the speed of lock-in time on changing frequency of the VCO through the divider setting. On can make the loop filter very slow and cut the (awful, terrible) spurious sidebands down...and also waste literal minutes waiting for the PLL to lock in. Those (awful, terrible) spurs at increments of the reference frequency are seldom worth worrying about in a PLL with good shielding and decoupling around the control voltage parts of the PLL. [the proof lies in tens of thousands of simple PLLs working all around the globe without worries over "not working" because their spurious outputs are "too high"] Len Anderson retired (from regular hours) electronic engineer person |
Wrong on all counts Len!
Not quite it. In order to derive a control voltage for the controlled oscillator, the PFD output MUST BE A FINITE WIDTH. In lock, at any frequency increment, the relative phase of the signal and reference is constant, stable, BUT THERE IS ALWAYS A PHASE OFFSET. This is necessary in order to derive the control voltage which keeps the VCO in lock. In the digital PFD, there are essentially two outputs that drive the charge storage circuit; "pump up" and "pump down". If there is a phase error, the corresponding output produces pulses that are exactly proportional to the time-error between the two PD inputs. If the time error corresponds to a leading phase relationship between VCO and reference, then the "pump down" output produces pulses equal in width to the lead time, discharging the charge storage element. If there is a lagging relationship, then the "pump up" output produces produces pulses equal in width to the lag time, charging the charge storage element. If there is no error , then neither pump output produces any pulses, and the charge storage element just 'holds' the last charge it had on it. In a practical PFD implementation, it is impossible to maintain the zero pulse-width point because the PFD is a digital feedback circuit, and you would need parts with zero propagation delay to make such a circuit. However, the width of the pulses in modern designs can get down into the nanosecond range at lock. For this reason, the PFD can produce much lower sideband content than the XOR, which outputs large pulses at lock. The larger the output pulse, the more difficult the loop filter design. No. In the '44-type PFD, the output pulses will be zero ONLY if the divided VCO is way off frequency, at one end of the controllable range or the other. IN LOCK the PFD output will ALWAYS HAVE A FINITE PULSE WIDTH at the reference frequency repetition rate. Without that pulse width averaged out there would be NO control voltage to hold the divided VCO within range. Wrong again! With large frequency errors, the PFD produces constant pumping. If it didn't, it couldn't acquire with phase errors larger than 180deg. You are also wrong in asserting that the lock-in range of the PFD is +/- 180 degrees. In fact, it is infinite (in theory). Yes, its linear output compliance range is +/- 180 degrees, but it can acquire lock even when there is an infinite frequency error. This is because once the PFD output exceeds it's compliance range, it outputs a constant "pump up" or "pump down" pulse train, which in turn causes the loop filter voltage to ramp up or down as the case might be until the signal comes back into the compliance range and lock is established. In practice the range is not infinite, only because you can't build a VCO with infinite tuning range or a PFD with infinite clocking speed. The XOR's big advantage is that it is simple, and there is no discontinuity around the phase lock point (as there is in the PFD), but it does not lock up readily in the face of frequency errors. The PFD's advantage is that it readily locks up, even in the face of large frequency errors and it also produces an easily filtered output. Joe W3JDR "Avery Fineman" wrote in message ... In article , "W3JDR" writes: John, Elsewhere in this thread there seems to have been some debate on the operation of the phase frequency detector. IMHO if the phase detector has a tri-state output then the loop over time must lock with no phase difference between the reference and controlled signals, ie 0 degrees. Theoretically, the edge controlled PFD locks the signal & reference with 0 degrees phase error. When the loop is locked, the output pulses from the PFD are theoretically infinitesimally small. However, neither the PFD chip nor the external charge pump/loop filter are perfect. Any leakage in the charge pump and/or loop filter causes the PFD to continually output wider than normal pulses in order to supply the additional charge current necessary to make up for the current leakage. This results in a non-zero phase error at the PFD inputs. Not quite it. In order to derive a control voltage for the controlled oscillator, the PFD output MUST BE A FINITE WIDTH. In lock, at any frequency increment, the relative phase of the signal and reference is constant, stable, BUT THERE IS ALWAYS A PHASE OFFSET. This is necessary in order to derive the control voltage which keeps the VCO in lock. It's a common misconception to think of phase lock or even phase control as trying to achieve a "zero degree" condition with no phase offset. What is achieved in phase lock is a STABLE, BUT OFFSET, phase relationship between signal and reference frequencies at PFD inputs. The easiest way to prove the condition is to scope an adjustable- frequency PLL at the signal and reference PFD inputs and then the '44-type PFD output into the loop filter. [measure the VCO frequency separately if desired to prove the VCO, if desired] At one locked frequency of the VCO the PFD output is a finite-width pulse at the reference frequency. Change the divider setting for a new VCO frequency and the PFD output has a different pulse width. That can be confirmed by the DC control voltage...one value at the first frequency setting, another value at the second frequency setting. That DC control voltage is, in effect, an average value of the pulse width out of the PFD. I am struggling to understand the comment above that the AD9901 is not suitable for use in frequency synthesizers because of the large spurious sidebands arising from its use. What causes the additional sidebands ? As mentioned, the PFD output pulses approach zero width at lock, making it easier to filter the pulses down to pure DC in the charge pump/loop filter. No. In the '44-type PFD, the output pulses will be zero ONLY if the divided VCO is way off frequency, at one end of the controllable range or the other. IN LOCK the PFD output will ALWAYS HAVE A FINITE PULSE WIDTH at the reference frequency repetition rate. Without that pulse width averaged out there would be NO control voltage to hold the divided VCO within range. The XOR PD will output a 50% duty cycle pulse train at lock. This is much more difficult to filter down to pure DC, resulting in modulation of the VCO, and thus sidebands. It is no different. Control voltage averaged out of an XOR phase detector is still from essentially the same finite pulse width. [those have worked for years without any comments about "spurs"] The vast difference between an XOR PD and the '44-type PFD is that the XOR PD is limited to a +/- 90 degree control and can't tell the loop how to come off of a start-up condition which is way off to one side of the VCO range or the other. The '44-type PFD works over +/- 180 degree range and DOES indicate a way-off VCO signal frequency condition. It will start up safely. In the old PDs limited to 90 degree range, the general way of starting up was with a very slow sawtooth generator algebraically adding to the control voltage...once the lock range was achieved, more circuitry shut off the sawtooth. [lots of extra parts] In either type of phase detector, the amount of reference frequency ripple out of the loop filter is dependent on the type of filter and the speed of lock-in time on changing frequency of the VCO through the divider setting. On can make the loop filter very slow and cut the (awful, terrible) spurious sidebands down...and also waste literal minutes waiting for the PLL to lock in. Those (awful, terrible) spurs at increments of the reference frequency are seldom worth worrying about in a PLL with good shielding and decoupling around the control voltage parts of the PLL. [the proof lies in tens of thousands of simple PLLs working all around the globe without worries over "not working" because their spurious outputs are "too high"] Len Anderson retired (from regular hours) electronic engineer person |
Wrong on all counts Len!
Not quite it. In order to derive a control voltage for the controlled oscillator, the PFD output MUST BE A FINITE WIDTH. In lock, at any frequency increment, the relative phase of the signal and reference is constant, stable, BUT THERE IS ALWAYS A PHASE OFFSET. This is necessary in order to derive the control voltage which keeps the VCO in lock. In the digital PFD, there are essentially two outputs that drive the charge storage circuit; "pump up" and "pump down". If there is a phase error, the corresponding output produces pulses that are exactly proportional to the time-error between the two PD inputs. If the time error corresponds to a leading phase relationship between VCO and reference, then the "pump down" output produces pulses equal in width to the lead time, discharging the charge storage element. If there is a lagging relationship, then the "pump up" output produces produces pulses equal in width to the lag time, charging the charge storage element. If there is no error , then neither pump output produces any pulses, and the charge storage element just 'holds' the last charge it had on it. In a practical PFD implementation, it is impossible to maintain the zero pulse-width point because the PFD is a digital feedback circuit, and you would need parts with zero propagation delay to make such a circuit. However, the width of the pulses in modern designs can get down into the nanosecond range at lock. For this reason, the PFD can produce much lower sideband content than the XOR, which outputs large pulses at lock. The larger the output pulse, the more difficult the loop filter design. No. In the '44-type PFD, the output pulses will be zero ONLY if the divided VCO is way off frequency, at one end of the controllable range or the other. IN LOCK the PFD output will ALWAYS HAVE A FINITE PULSE WIDTH at the reference frequency repetition rate. Without that pulse width averaged out there would be NO control voltage to hold the divided VCO within range. Wrong again! With large frequency errors, the PFD produces constant pumping. If it didn't, it couldn't acquire with phase errors larger than 180deg. You are also wrong in asserting that the lock-in range of the PFD is +/- 180 degrees. In fact, it is infinite (in theory). Yes, its linear output compliance range is +/- 180 degrees, but it can acquire lock even when there is an infinite frequency error. This is because once the PFD output exceeds it's compliance range, it outputs a constant "pump up" or "pump down" pulse train, which in turn causes the loop filter voltage to ramp up or down as the case might be until the signal comes back into the compliance range and lock is established. In practice the range is not infinite, only because you can't build a VCO with infinite tuning range or a PFD with infinite clocking speed. The XOR's big advantage is that it is simple, and there is no discontinuity around the phase lock point (as there is in the PFD), but it does not lock up readily in the face of frequency errors. The PFD's advantage is that it readily locks up, even in the face of large frequency errors and it also produces an easily filtered output. Joe W3JDR "Avery Fineman" wrote in message ... In article , "W3JDR" writes: John, Elsewhere in this thread there seems to have been some debate on the operation of the phase frequency detector. IMHO if the phase detector has a tri-state output then the loop over time must lock with no phase difference between the reference and controlled signals, ie 0 degrees. Theoretically, the edge controlled PFD locks the signal & reference with 0 degrees phase error. When the loop is locked, the output pulses from the PFD are theoretically infinitesimally small. However, neither the PFD chip nor the external charge pump/loop filter are perfect. Any leakage in the charge pump and/or loop filter causes the PFD to continually output wider than normal pulses in order to supply the additional charge current necessary to make up for the current leakage. This results in a non-zero phase error at the PFD inputs. Not quite it. In order to derive a control voltage for the controlled oscillator, the PFD output MUST BE A FINITE WIDTH. In lock, at any frequency increment, the relative phase of the signal and reference is constant, stable, BUT THERE IS ALWAYS A PHASE OFFSET. This is necessary in order to derive the control voltage which keeps the VCO in lock. It's a common misconception to think of phase lock or even phase control as trying to achieve a "zero degree" condition with no phase offset. What is achieved in phase lock is a STABLE, BUT OFFSET, phase relationship between signal and reference frequencies at PFD inputs. The easiest way to prove the condition is to scope an adjustable- frequency PLL at the signal and reference PFD inputs and then the '44-type PFD output into the loop filter. [measure the VCO frequency separately if desired to prove the VCO, if desired] At one locked frequency of the VCO the PFD output is a finite-width pulse at the reference frequency. Change the divider setting for a new VCO frequency and the PFD output has a different pulse width. That can be confirmed by the DC control voltage...one value at the first frequency setting, another value at the second frequency setting. That DC control voltage is, in effect, an average value of the pulse width out of the PFD. I am struggling to understand the comment above that the AD9901 is not suitable for use in frequency synthesizers because of the large spurious sidebands arising from its use. What causes the additional sidebands ? As mentioned, the PFD output pulses approach zero width at lock, making it easier to filter the pulses down to pure DC in the charge pump/loop filter. No. In the '44-type PFD, the output pulses will be zero ONLY if the divided VCO is way off frequency, at one end of the controllable range or the other. IN LOCK the PFD output will ALWAYS HAVE A FINITE PULSE WIDTH at the reference frequency repetition rate. Without that pulse width averaged out there would be NO control voltage to hold the divided VCO within range. The XOR PD will output a 50% duty cycle pulse train at lock. This is much more difficult to filter down to pure DC, resulting in modulation of the VCO, and thus sidebands. It is no different. Control voltage averaged out of an XOR phase detector is still from essentially the same finite pulse width. [those have worked for years without any comments about "spurs"] The vast difference between an XOR PD and the '44-type PFD is that the XOR PD is limited to a +/- 90 degree control and can't tell the loop how to come off of a start-up condition which is way off to one side of the VCO range or the other. The '44-type PFD works over +/- 180 degree range and DOES indicate a way-off VCO signal frequency condition. It will start up safely. In the old PDs limited to 90 degree range, the general way of starting up was with a very slow sawtooth generator algebraically adding to the control voltage...once the lock range was achieved, more circuitry shut off the sawtooth. [lots of extra parts] In either type of phase detector, the amount of reference frequency ripple out of the loop filter is dependent on the type of filter and the speed of lock-in time on changing frequency of the VCO through the divider setting. On can make the loop filter very slow and cut the (awful, terrible) spurious sidebands down...and also waste literal minutes waiting for the PLL to lock in. Those (awful, terrible) spurs at increments of the reference frequency are seldom worth worrying about in a PLL with good shielding and decoupling around the control voltage parts of the PLL. [the proof lies in tens of thousands of simple PLLs working all around the globe without worries over "not working" because their spurious outputs are "too high"] Len Anderson retired (from regular hours) electronic engineer person |
In article , "W3JDR"
writes: Wrong on all counts Len! Not quite it. In order to derive a control voltage for the controlled oscillator, the PFD output MUST BE A FINITE WIDTH. In lock, at any frequency increment, the relative phase of the signal and reference is constant, stable, BUT THERE IS ALWAYS A PHASE OFFSET. This is necessary in order to derive the control voltage which keeps the VCO in lock. In the digital PFD, there are essentially two outputs that drive the charge storage circuit; "pump up" and "pump down". If there is a phase error, the corresponding output produces pulses that are exactly proportional to the time-error between the two PD inputs. If the time error corresponds to a leading phase relationship between VCO and reference, then the "pump down" output produces pulses equal in width to the lead time, discharging the charge storage element. If there is a lagging relationship, then the "pump up" output produces produces pulses equal in width to the lag time, charging the charge storage element. If there is no error , then neither pump output produces any pulses, and the charge storage element just 'holds' the last charge it had on it. Going to make it one of those long days? :-) OK, so where is the VCO control voltage coming from and how does it "know" how to reach the right voltage for the right frequency? It doesn't...because the PFD output (MC4044 type) does not have to. There will ALWAYS be a small error in any control loop... otherwise a control loop couldn't function to do controlling (basic control loop theory which so many seem to forget). A "charge pump" is basically a voltage-to-current converter to develop a basically-DC control voltage for the VCO of the PLL after the loop filtering. One doesn't need to use the charge pump in the MC4044 or the 11C44 chip. The digital output of the PFD can go direct to the loop filter. Even with the charge pump in-use, the whole thing (pump and loop filter or integrator/ filter) simply integrates a time variation (width of repetitious pulses out of PFD) into a stable DC value. In a practical PFD implementation, it is impossible to maintain the zero pulse-width point because the PFD is a digital feedback circuit, and you would need parts with zero propagation delay to make such a circuit. Absolutely not. There must be SOME gate delay. If there were zero, then every single D or J-K flip-flop would not work! Since they do work, there is always SOME internal gate delay. That internal IC capacitance causing the delay is the cause for all that heat-dissipation effort on hundred-thousand-plus transistor junction ICs used in single-chip microcomputers. In a 9- or 10-gate IC there isn't a lot of heat rise...but the parasitic gate structure capacitance is always there and all gates have finitie propagation delays. Some number of years ago I went into the old databooks (so far back they were free for anyone and still had the equivalent circuits in them...like thirty plus years ago) and started doing timing diagrams to see EXACTLY how they worked. Most interesting bit of "reverse engineering" and also quite interesting. The '44-type PFD digital part is essentially a very complex D FF like structure and it triggers only one direction of transition edges (like the Ds and J-Ks). The '44 is more complex in trying to see how it works due to the various conditions of relative input phases. If there are more than two signal edges for every reference edge, the outputs hold at one state indicating a "way-off" towards the high frequency range end of the signal. If there are more than two reference edges for every signal edge, the outputs flip to the other state...the "way-off" signal frequency is too low. However, when there is one input edge for each other input edge, the outputs produce a variable-width pulse, repetition rate equal to the reference frequency, which corresponds to the relative phase of the two inputs. The outputs are always "flipping" when the inputs are at the same frequency even though the inputs need NOT be in exact phase positioning. Not a problem. That variable width turns out to be extremely good for control since a simple integrator can convert the variable time into a variable voltage whose DC value is proportional to the relative inputs phase displacement. An op-amp integrator circuit functions as a sort of time-to-current- to-output-voltage converter (technically, the input R is creating a pseudo-constant-current source for the mid-point of R and C of the integrator op-amp input). That can also be used as a "Type 1" loop filter. With some modifications of a basic integrator, it can become any of the other types. Or, one can, with a sensitive control voltage characteristic of the VCO, use a passive loop filter with the filter input directly on the PFD output (choose either one to go with polarity of the VCO control needed). For that alternate condition, the PFD Vcc *MUST* be stable and decoupled less it mess around with more badness in the control voltage. The "charge pump" circuit of the MC4044/11C44 is really optional to use. It isn't absolutely necessary although it can cut down on the number of parts used. Based on hands-on observation of several of these PLLs, especially those of PFDs made from individual logic gates, the PFD outputs ARE pulses at the reference frequency repetition rate. Their width is proportional to the integrated-averaged DC control voltage of the VCO when in lock. If what you say is true, then there would be ZERO control voltage out of any of the mentioned interface circuits. Obviously, there must be some finite amount of control voltage for the VCO to adjust to a particular PLL frequency increment. That control voltage is the integrated-averaged DC out of the loop filter, not some mythical "charged whatsis" from that charge pump. In looking at the relative phases of the signal and reference AC inputs, the loop is LOCKED even though the phases are offset. The phases remain "in step" and unchanging on the 'scope but they are offset in phase from one another. [that's normal with this kind of PFD and PLL] I've been looking at these things for about three decades and see the same things. With the MC145151 combo PLL chip I'm playing with now, the PFD gates aren't fully available for peeking, but it locks in as advertised as I said above. However, the width of the pulses in modern designs can get down into the nanosecond range at lock. Nobody, not even the PLL really cares. How much voltage are you going to generate on the VCO control line from nanosecond pulse widths at a 1 KHz reference input repetition rate? Very little. For this reason, the PFD can produce much lower sideband content than the XOR, which outputs large pulses at lock. The larger the output pulse, the more difficult the loop filter design. The only thing "difficult" about a PLL is others paying attention to the REQUIRED values of control voltage gain and the reference frequency AND the simple math needed to calculate those values. "Difficult" is when the control voltage isn't linear over frequency (which upsets the heck out of the control gain at one end of the VCO range). "Difficult" is not paying attention to the subcircuit isolation and shielding and decoupling that produces the control voltage where it is ripe for picking up garbage that results in all kinds of badness in VCO stability. No. In the '44-type PFD, the output pulses will be zero ONLY if the divided VCO is way off frequency, at one end of the controllable range or the other. IN LOCK the PFD output will ALWAYS HAVE A FINITE PULSE WIDTH at the reference frequency repetition rate. Without that pulse width averaged out there would be NO control voltage to hold the divided VCO within range. Wrong again! With large frequency errors, the PFD produces constant pumping. If it didn't, it couldn't acquire with phase errors larger than 180deg. No. If you examine the states of all gates in a '44 PFD with corresponding input waveform states, you will see that the "way-off" (phase errors larger than 180 degrees) conditions of the PFD outputs REMAIN in their fully-on or fully-off states. That's the gem of this gate arrangement and the key to coming into lock on power-up. One reason I submitted my article to Jim Fisk at Ham Radio magazine (it was not in the original sequence at the start of that series) was as a result of trying to explain the gate-states of the '44 PFD to another. The waveform timing diagrams in that September 1982 article accurately show the state changes (without the precise amount of internal gate delay, not really needed in explanation). Just to make certain, I'd duplicated the gate logic in an Apple ][ program to make sure...and to see the variations in original conditions that might cause a bad start-up. I didn't use the conventional bubble-and-arrow state change diagrams since so few contemporaries could "read" them and I didn't much care for that kind of presentation either. Waveforms were an old familiar thing and I stuck with that. You are also wrong in asserting that the lock-in range of the PFD is +/- 180 degrees. In fact, it is infinite (in theory). "Infinite" only in the grossest sense of being - in effect - locked up on either of the "way-off" conditions. From what I gather, it was designed to do that very thing. An excellent thing to insure start-up. However, integrated-averaged to DC, the outputs of the PFD make an excellent phase meter with a DC that can be converted to binary in an A-to-D. The Rocketdyne Deformable Mirror project used that characteristic to measure the heterodyned optical signals from the optics at 1 MHz PFD input. It worked just fine out to about +/- 179 degrees or so when calibrated for the whole optical-electronic loop. [optics could approach 180 but never quite get exactly there...but then that's difficult with electronics also, needing time-interval averaging counters and such which we DID use...but the optics folks wanted to tweak their stable table optics more than tweaking instrument dials...:-)] Yes, its linear output compliance range is +/- 180 degrees, but it can acquire lock even when there is an infinite frequency error. This is because once the PFD output exceeds it's compliance range, it outputs a constant "pump up" or "pump down" pulse train, which in turn causes the loop filter voltage to ramp up or down as the case might be until the signal comes back into the compliance range and lock is established. No. At beyond-control-range input frequencies, the PFD outputs go to their stable, unchanging "way-off" states and stay there until both inputs are the same frequency. Ain't no "pump" pulses whatsoever at those "way-off" conditions. The XOR's big advantage is that it is simple, and there is no discontinuity around the phase lock point (as there is in the PFD), but it does not lock up readily in the face of frequency errors. The PFD's advantage is that it readily locks up, even in the face of large frequency errors and it also produces an easily filtered output. In practice, since the last days of WW2, phase-frequency control loops have used lots of extra circuitry to cure that start-up. Philco did that with some S-band microwave radio relay gear used by the USAF in 1955. Army used L-band crystal-controlled microwave radio relay terminals by GE, had no problems. USAF had Philco tech reps there seemingly all the time since their frequency control tended to pop off lock and go sweeping frequency a lot from their extra sawtooth circuitry. [PLL was first disclosed in 1932 by "H. de Bellecize, working in France" according to my giant 1980 50th anniversary special edition of Electronics magazine] There have been a few PFD circuits devised before the '44 type but I'd say the '44 went all the way to excellence with elegance in its simplicity. There have been at least one close to the '44 but arranged differently and with more internal parts...but that one works about the same as the '44. When you get the chance, grab a 'scope and look into the waveforms of a PFD as well as the control voltage. You will find out I'm right. No "theory" on that, just working PLL hardware. I've seen and observed that, used the basic knowledge to build my own PLLs (including a couple just for me) and am confident in the explanation I gave. They WORK by all the nice instruments from Hewlett and Packard (rest their souls). Len Anderson retired (from regular hours) electronic engineer person |
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